PRELIMINARY
NetPHY-4LP-KT/12PT
12-Port Demonstration Kit for the Am79C875
DISTINCTIVE CHARACTERISTICS
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Evaluation board is con鏗乬ured for layout
demonstration
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Compact step-and-repeat design ideal for multi-
port applications
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Quad magnetics modules with 12-port RJ-45
dual-stack connector
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Single VDD plane, single VSS plane, with
appropriate decoupling capacitors
GENERAL DESCRIPTION
The NetPHY鈩?4LP Demonstration Kit provides an
easy-to-use tool for demonstrating the ease of design
and layout using the NetPHY-4LP Low Power Quad 10/
100 Ethernet Transceiver. This non-functional board
will show how easy it is for system designers to create
a four-port layout and to step-and-repeat the layout for
any number of ports (in multiples of 4). 24-, 36-, and 48-
port switch systems can easily be created without the
need for individual routing and layout, as traditionally
required.
The NetPHY-4LP demonstration board shows an ac-
tual layout for a 12-port system. The small size of each
NetPHY-4LP device results in signi鏗乧ant board space
savings against other quad PHY devices, even against
hex and octal PHYs. Because the NetPHY-4LP is opti-
mized for RMII switch applications, the package size is
drastically reduced to a 100-pin standard PQFP pack-
age. RMII reduces the number of pins required at the
PHY/ASIC interface to 7 pins per port. This is a savings
of 9 pins per port from the legacy MII interface. Less
pins also means lower pin and package costs for
ASICs.
The NetPHY-4LP device is pin-placement optimized for
switch applications. The RMII pins are located on the
side that interfaces to the ASIC, requiring very short
traces and minimizing outside interference that can af-
fect high-speed signals. Also, LED and con鏗乬uration
pins are placed on the sides of the NetPHY-4LP pack-
age, away from the high-speed data and control pins,
which they would affect otherwise. Furthermore, all the
transmit and receive differential pairs are located on
the magnetics side, and traces are very short and
direct to minimize signal attenuation.
To demonstrate compact layout and placement, the
NetPHY-4LP demonstration board provides the layout
from the PHY to the dual-stack RJ-45 connector, which
is the setup that more closely resembles what is used
in today鈥檚 system boxes. It is imperative that the layout
be clean and concise, since any kind of interference
signi鏗乧antly affects signal conditions. Therefore, the
layout provided in the demonstration kit is the most op-
timal in terms of noise and connectivity.
KIT CONTENTS
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NetPHY-4LP Demonstration board
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Schematics
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Bill of Materials
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Board artwork for all layers
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NetPHY-4LP device data sheet (PID 22236B)
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci-
鏗乧ations and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in-
tellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, 鏗乼ness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
Trademarks
Copyright 漏 1999 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof, and HomePNA and PCnet are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identi鏗乧ation purposes only and may be trademarks of their respective companies.
Publication #
22360
Rev:
A
Amendment/0
Issue Date:
April 1999
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