SC300 microcontroller system can provide jumpers that allow BIOS/system firmware to
load and run from a linear memory card in a PCMCIA socket instead of from the on-board boot
ROM. On systems with soldered-down boot ROMS, these jumper provisions are useful for boot
ROM development or any situation where the boot ROM may be corrupted. This application note
describes the issues involved in using this boot-from-PCMCIA feature on an 脡lanSC300
microcontroller design.
address lines SA23鈥揝A0. The fetch address will
register. At that time, if the microcontroller is in
lowest 1 Mbyte (0xxxxx). On reset, addresses in the
range FF0000鈥揊FFFFF (FFxxxx) and 0F0000鈥?/div>
0FFFFF (0Fxxxx) always assert ROMCS and are
default 8-bit accesses.
Note that on most 脡lanSC300 microcontroller systems
based on an AT-compatible BIOS, the boot code does
a far jump in real mode to an address in the 0Fxxxx
range, and the boot ROM is a 64- or 128-Kbyte device
that only looks at the low 16 or 17 address bits. On
such systems, FFxxxx and 0Fxxxx in ROMCS space
will map to the same ROM device.
A PCMCIA memory card can have two 64-Kbyte
address spaces addressed (attribute and common
memory) using 26 address lines and a REG line, which
selects one of the two address spaces. Data widths of
either 16 or 8 bits are supported using low and high
byte select (CEL and CEH). Either an OE line is
asserted to indicate a read, or a WE line is asserted to
indicate a write.
On the 脡lanSC300 microcontroller, the PCMCIA
address lines A23鈥揂0 are the same as the system
address lines SA23鈥揝A0, while PCMCIA address lines
A25 and A24, which are controlled by CA24鈥揅A25
control registers 1鈥? (indexes B5h鈥揃7h), are unique to
PCMCIA. The PCMCIA data lines, D15鈥揇0, are the
same as system data lines SD15鈥揝D0. For PCMCIA
OE and WE, the 脡lanSC300 microcontroller can be
programmed using bit 4 in the Miscellaneous 3
Register (Index BAh) to assert either MEMR and
MEMW on PCMCIA accesses or to assert PCMCOE
and PCMCWE. (PCMCOE and PCMCWE take over
pins 84 and 89 that are normally part of the parallel port
interface. They are useful in systems that need to
distinguish between PCMCIA accesses and ISA
accesses and do not use the parallel port.)
On 脡lanSC300 microcontroller designs that use
buffered PCMCIA slots, the ICDIR pin can be used to
tell the buffer whether it should accept data or drive
data. Unbuffered PCMCIA designs do not use the
ICDIR signal. At reset, the ICDIR pin from the
脡lanSC300 microcontroller is driven High, indicating
that the buffers should accept data rather than drive
data. ICDIR then remains High at all times unless the
microcontroller is doing a PCMCIA read.
JUMPERS TO ENABLE BOOT FROM PCMCIA
Chip Select
Because ROMCS will be asserted at boot time, there
must be a jumper that breaks the path of ROMCS from
the microcontroller to the CS of the boot ROM, and the
path of MCEL_A from the microcontroller to CEL of the
PCMCIA socket. Then, the jumper must route ROMCS
from the microcontroller to CEL of the PCMCIA socket.
This will tell the PCMCIA card to place the addressed
byte, whether from an even or odd address, on D7鈥揇0,
just as in an 8-bit ROM access. An example is shown
in Figure 1. Jumper Configurations. For normal
operation, there are jumpers from 1 to 2 and from 3 to
4. For boot from PCMCIA operation, there is a jumper
from 2 to 3.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
21824
Rev:
A
Amendment/0
Issue Date:
July 1997
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