脡lan
TM
SC300 and 脡lanSC310 Microcontrollers
Memory Management
Application Note
The 脡lan
TM
SC300 and 脡lanSC310 microcontrollers contain a sophisticated memory management
unit (MMU), which makes PC/AT compatibility easy to achieve. However, if you wish to stray from
the standard path and do something different, there is much to be learned concerning the
capabilities and limitations of the MMU. The purpose of this application note is to explain what the
MMU is capable of and how it may be programmed to achieve your goals. This document
supplements
Chapter 2, Memory and PCMCIA Management
of the
脡lan
TM
SC300 Microcontroller
Programmer鈥檚 Reference Manual
, order #18470.
INTRODUCTION
Unless otherwise noted, the features discussed in this
document for the 脡lan
TM
SC300 microcontroller apply
equally to the 脡lan
TM
SC310 microcontroller. The term
鈥淒RAM鈥?will be used to mean either DRAM or SRAM.
SRAM for system memory is an option on the
脡lanSC300 microcontroller and for the purposes of
memory management, SRAM is treated identically to
DRAM. The term 鈥淟ocal/ISA Bus鈥?includes both Local
bus and ISA bus cycles. These are treated identically
for memory management. When the 脡lanSC300
microcontroller is configured in full ISA mode or in
internal LCD mode, all accesses are treated as ISA bus
cycles. When the 脡lanSC300 microcontroller is
configured in local bus mode, the local bus is first given
the cycle, and if a local bus peripheral accepts the
cycle, the ISA bus never sees it. If no local bus
peripheral accepts the cycle, it is stretched into a
slower ISA cycle, and MEMR or MEMW is asserted.
16 Mbyte of memory at a time. This 16 Mbyte of
memory is aliased 256 times into the 4-Gbyte physical
address space of the Am386 processor. Although it is
tr ue th at th e PCM CIA add re ss sp ac es of th e
脡lanSC300 microcontroller support 26 bits (64 Mbyte),
these PCMCIA spaces are only accessible by
translated memory management.
Behavior at Reset and SMI
After reset or when processing a system management
interrupt (SMI), the CPU executes from the top of
memory. The processor is in Real mode and normally
can address only 1 Mbyte, but the first instruction is
fetched from address FFFFF0 at the top of memory.
The initial value of the code segment, CS, is F000, and
the initial value of the instruction pointer, IP, is FFF0.
However, the internal CPU base address associated
with the code segment is FF0000 rather than F0000.
The processor can remain in this top 64 Kbytes of the
available system memory address space by making
near calls/jumps. If a far call/jump is executed and the
CPU is still in Real mode at the time of this far control
transfer, the far control transfer will cause the CS base
address to be set to 16 times the segment of the jump
target. This is the normal Real mode behavior. Thus,
the target of such a far jump must be in the lower 1
Mbyte. Many PC/AT-compatible BIOS implementations
have a far jump to a target in segment F000 as the first
instruction executed.
The fact that the physical address of the code executed
at reset is nowhere near the physical address of the
code executed at the target of the first Real mode far
jump can be important for systems with boot ROMs
larger than 1 Mbyte. This is discussed in the section
entitled ROMCS Space and Non-Translated Memory
Management.
Note that the behavior described previously applies to
SMI handling as well as to reset. In both cases, you
should ensure that the target of any far jump is mapped
appropriately. For example, at FFFFF0, a system may
Publication#
21823
Rev:
A
Amendment/0
Issue Date:
July 1997
ADDRESS DECODING AND ALIASING
Most designers are familiar with address aliasing,
which simply means that if an address is only partially
decoded by a device, that device will appear to exist
multiple times throughout the address space. The
following topics that are associated with aliasing on the
脡lanSC300 microcontroller must be thoroughly
understood by the designer before attempting to use
the 脡lanSC300 microcontroller memory management.
Aliasing within the 4-Gbyte Address
Space of the Am386
廬
Microprocessor
The core CPU of the 脡lanSC300 microcontroller is an
Am386SX microprocessor, which supports 24 physical
address lines (16 Mbyte of physical address space).
The Am386 microprocessor architecture supports 32
bits of addressing, but the top 8 address bits from the
CPU are effectively ignored for all memory mapping
functions. From a programming perspective, this
means that the 脡lanSC300 microcontroller can 鈥渟ee鈥?/div>
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
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