Troubleshooting Micro Power Off Mode on
脡lan
TM
SC300 and 脡lanSC310 Microcontrollers
and Evaluation Boards
Application Note
by Cliff Grant
Micro Power Off mode is a power management mode that allows you to maintain the system date,
time, and configuration data when the rest of the system is powered down. This application note
addresses some issues regarding Micro Power Off mode. The information in this application note
is intended to be used in addition to the documents listed in the Reference Materials section at the
end of the application note. The information discussed here applies equally to both 脡lan
TM
SC300
and 脡lanSC310 microcontrollers. Note that this application note refers specifically to revision D of
the
脡lan
TM
SC300 Microcontroller Data Sheet
, order #18514 and revision B of the
脡lan
TM
SC300
Microcontroller Programmer鈥檚 Reference Manual
, order #18470.
MICRO POWER OFF MODE TIMING AND
POWER REQUIREMENTS
Micro Power Off mode allows you to remove power
from the VCC1, VSYS, VSYS2, VCC5, and, optionally,
VMEM power inputs to the 脡lan
TM
SC300
microcontroller. This allows the RTC timer and RAM
contents to be kept valid by using a battery back-up
power source on the VCC core and AVCC (analog
VCC) pins, which typically should use only 25
碌A(chǔ)
in this
mode.
The system should not be powered up directly into
Micro Power Off mode. As described on page 59 of the
脡lan
T M
SC300 Microcontroller Data Sheet
, order
#18514D, the system must be allowed to fully power up
into High-Speed (HS) mode upon initial power
application of any power source. Because a battery
has insufficient power for the 脡lanSC300
microcontroller to initialize in HS mode, the system
design must first power up the 脡lanSC300
microcontroller from the main power source, and not
allow the chip to be powered from the battery until after
it is fully initialized in HS mode and properly
tr ans i tio ned in to M ic r o P owe r Off m od e. The
脡lan
TM
SC300 and 脡lan
TM
SC310 Microcontrollers
Solution For Systems Using A Back-Up Battery
Application Note
, order #20746, describes a circuit that
is intended to gate the battery off of the 脡lanSC300
microcontroller until after the system has been
initialized from the main power source.
The timing sequence and specifications for
powering-up, entering, and exiting Micro Power Off
mode described on pages 99鈥?01 of the 脡lanSC300
microcontroller data sheet must be met. Be sure to
observe the power-up (and power-down) voltage
sequencing specifications listed in the Notes section at
the bottom of Table 51 on page 99 of the 脡lanSC300
microcontroller data sheet.
Refresh can be either enabled or disabled during Micro
Power Off mode, and the VMEM power can be
optionally removed, provided that either the memory is
also powered off or all DRAM interface signals are kept
at 0 V. Note that there are two possible timing
sequences shown on page 101 for entering Micro
Power Off mode with or without DRAM refresh
enabled. For documentation showing an external
workaround for disabling DRAM refresh prior to
entering Micro Power Off mode, refer to Errata #EB30
(available by contacting your AMD FAE).
RSTDRV SIGNAL TIMING
As described on page 58 of the 脡lanSC300
microcontroller data sheet, the RSTDRV signal is High
True output of the 脡lanSC300 microcontroller and is a
function of the internal core鈥檚 reset state, the state of
the RESIN and IORESET signals, and the value for the
PLL start-up timer in the Clock Control Register (Index
8Fh). Figures 32 and 33 on page 100 of the 脡lanSC300
data sheet provide timing information for the RSTDRV
signal.
PROGRAMMER鈥橲 REFERENCE MANUAL
In a brief discussion about Off mode on page 1-7, the
脡 l a n
T M
S C 3 0 0 M i c r o c o n t r o l l e r P r o g r a m m e r 鈥檚
Reference Manual,
order #18470B, states, "The
system cannot be programmed to enter Off mode
directly. The only method of Off mode entry is by
expiration of the Suspend to Off Mode Timer Register
at Index 87h."
In the Micro Power Off Mode section on page 1-40, the
manual states, "There is no software processing
required or available to enter the Micro Power Off
mode. For most applications, Micro Power Off mode is
Publication#
21810
Rev:
B
Amendment/0
Issue Date:
October 1997
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
1
2
3
4
5
