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21555-AA Datasheet

  • 21555-AA

  • Controller Miscellaneous - Datasheet Reference

  • 450.87KB

  • 30頁

  • ETC

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21555 Non-Transparent PCI-to-PCI
Bridge
Datasheet
Product Features
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Full compliance with the
PCI local Bus
Specification,
Revision 2.2, plus:
鈥?PCI Power Management support
鈥?Vital Product Data (VPD) support
鈥?CompactPCI Distributed Hot-Swap
support
3.3-V operation with 5.0-V tolerant I/O
Selectable asynchronous or synchronous
primary and secondary interface clocks
Concurrent primary and secondary bus
operation
Fully compliant with the
Advanced
Configuration Power Interface
(ACPI)
specification
Fully compliant with the
PCI Bus Power
Management
specification
Queuing of multiple transactions in either
direction
256 bytes of posted write (data and
address) buffering in each direction
256 bytes of read data buffering in each
direction
Four delayed transaction entries in each
direction
Two dedicated I2O delayed transaction
entries
Two sets of standard PCI Configuration
registers corresponding to the primary and
secondary interface; each set is accessible
from either the primary or secondary
interface
Direct offset address translation for
downstream memory and I/O transactions
Hardware enable for secondary bus central
functions
IEEE Standard 1149.1 boundary-scan
JTAG interface
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Four primary interface base address
configuration registers for downstream
forwarding, with size and prefetchability
programmable for all four address ranges
Three secondary interface address
configuration registers specifying local
address ranges for upstream forwarding,
with size and prefetchability programmable
for all three address ranges
Inverse decoding above the 4 GB address
boundary for upstream DACs
Ability to generate Type 0 and Type 1
configuration commands on the primary or
secondary interface via configuration or I/O
CSR accesses
Ability to generate I/O commands on the
primary or secondary interface via I/O CSR
accesses
I2O message unit
Doorbell registers for software generation
of primary and secondary bus interrupts, 16
bits per interface
Eight Dwords of scratchpad registers
Generic own bit (can memory-map)
semaphore
Parallel flash ROM interface with primary
bus expansion ROM base address register
Serial ROM interface
Secondary bus arbiter support for up to
nine external devices at 33 MHz and up to
four external devices at 66 MHz (in
addition to the 21555)
Secondary bus clock output for
synchronous operation
Four 32-bit base address configuration
registers mapping the 21555 control and
status registers (CSRs)
Available in 33 MHz and 66 MHz versions
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 278320-002

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