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20668 Datasheet

  • 20668

  • ?lanSC300 Data Sheet ?lanSC310 Data Sheet

  • 119頁(yè)

  • ETC

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PRELIMINARY
脡lan
鈩?/div>
SC310
Single-Chip, 32-Bit, PC/AT Microcontroller
n
Integrated memory controller
鈥?Controls symmetrically addressable DRAM or
asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit
DRAM or SRAM as main memory
鈥?Zero wait-state access with 70 ns, Page mode
DRAMs
鈥?Supports up to 16 Mbyte system memory
鈥?Supports up to 16 Mbyte of application ROM/
Flash, and 320 Kbyte direct ROM BIOS access.
Also supports shadow RAM
鈥?Fully PC/AT compatible
n
Integrated PC/AT-lompatible leripheral logic
鈥?One programmable interval timer (fully 8254
compatible)
鈥?Two programmable interrupt controllers (8259A
compatible)
鈥?Two DMA controllers (8237A compatible)
鈥?Built-in real-time clock (146818A compatible),
with an additional 114 bytes of RAM
鈥?Internal Phase-Locked Loops (PLL) generate all
clocks from single 32.768 kHz crystal input
n
Bus configurations
鈥?16-bit data path
鈥?Optional bus configurations:
鈥?386 Local Bus mode with subset ISA
鈥?Maximum ISA Bus mode
鈥?Four programmable chip selects
鈥?Built-in 8042 chip select
n
Serial port controller (16450 UART compatible)
n
Bidirectional parallel port (EPP compliant)
DISTINCTIVE CHARACTERISTICS
n
Highly integrated, single-chip CPU and system
logic
鈥?Optimized for embedded PC applications
鈥?Combines 32 bit, x86 compatible, low-voltage
CPU with memory controller, PC/AT peripheral
controllers, real-time clock, and PLL clock
generators
鈥?0.7 micron, low-voltage, CMOS process, fully
static
n
Enhanced Am386
廬
SXLV CPU core
鈥?25 MHz or 33 MHz operating frequencies
鈥?3.3 V core, 3.3 V or 5 V memory and I/O
鈥?Low-power, fully static design for long battery life
鈥?System Management Mode (SMM) for power
management control
n
Integrated power management functions
鈥?Internal clock generators (using multiple Phase-
Locked Loops and one external 32-KHz crystal)
鈥?Supports CPU System Management Mode
(SMM)
鈥?Multiple operating modes: High Speed PLL, Low
Speed PLL, Doze, Sleep, Suspend, and Off. Fully
static design allows stopped clock.
鈥?Comprehensive control of system and peripheral
clocks
鈥?Five external power management control pins
鈥?Suspend refresh of DRAM array
鈥?Clock switching during ISA cycles
鈥?Low power consumption: 0.12 mW typical
Suspend mode power
鈥?Simultaneous multiple-voltage I/O pads operate
at either 3.3 V or 5 V. Core operates at 3.3 V for
minimum power consumption.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product
without notice.
Publication#
20668
Rev:
B
Amendment/0
Issue Date:
October 1997

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