鈥?/div>
5 taps of equal delay increment
Delays to 200ns
Low profile
Epoxy encapsulated
Meets or exceeds MIL-D-23859C
GND
IN
T1
T2
1
2
3
4
8
7
6
5
GND
T5
T4
T3
data
3
廬
delay
devices,
inc.
PACKAGES
IN
Signal Input
T1-T5 Tap Outputs
GND Ground
Note: Standard pinout shown
Other pinouts available
FUNCTIONAL DESCRIPTION
The 1516-series device is a fixed, single-input, five-
output, passive delay line. The signal input (IN) is
reproduced at the outputs (T1-T5) in equal increments.
The delay from IN to T5 (T
D
) and the characteristic
impedance of the line (Z) are determined by the dash
number. The rise time (T
R
) of the line is 30% of T
D
, and
the 3dB bandwidth is given by 1.05 / T
D
. The device is
available in a 8-pin DIP (1516) or a 8-pin SMD (1516S),
and a wide range of pinouts may be specified.
Part numbers are constructed according to the scheme
shown at right. For example, 1516C-101-500B is a 290
mil DIP, 100ns, 50鈩?delay line with pinout code B.
Similarly, 1516SB-151-501 is a 240 mil SMD, 150ns,
500鈩?delay line with standard pinout.
PART NUMBER CONSTRUCTION
1516(S)m - xxx - zzz p
MOUNTING HEIGHT CODE
See Table
DELAY TIME
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
IMPEDANCE
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
PINOUT CODE
See Table
Omit for STD pinout
SERIES SPECIFICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Dielectric breakdown:
Distortion @ output:
Operating temperature:
Storage temperature:
Temperature coefficient:
50 Vdc
10% max.
-55擄C to +125擄C
-55擄C to +125擄C
100 PPM/擄C
T
D
(ns)
5
10
15
20
25
30
40
50
60
75
80
100
110
125
150
180
200
T
I
(ns)
1.0
2.0
3.0
4.0
5.0
6.0
8.0
10.0
12.0
15.0
16.0
20.0
22.0
25.0
30.0
36.0
50.0
DELAY SPECIFICATIONS
T
R
(ns)
3.0
4.0
5.0
6.0
7.0
10.0
13.0
15.0
20.0
25.0
26.0
30.0
32.0
40.0
50.0
60.0
70.0
Z=50鈩?/div>
鈩?/div>
N/A
3
3
3
3
3
3
3
3
3
4
4
4
4
N/A
N/A
N/A
ATTENUATION (%) TYPICAL
Z=100鈩?Z=200鈩?Z=300鈩?Z=500鈩?/div>
鈩?/div>
鈩?/div>
鈩?/div>
鈩?/div>
5
N/A
N/A
N/A
5
5
N/A
N/A
5
5
N/A
N/A
5
5
5
N/A
5
5
5
7
5
5
5
7
5
5
5
7
5
5
7
7
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
8
10
10
7
8
10
10
8
10
12
12
PINOUT CODES
CODE
STD
A
B
C
D
IN
2
1
1
7
1
T1
3
2
7
2
2
T2
4
3
3
6
7
T3
5
4
6
3
3
T4
6
6
4
5
6
T5
7
7
5
4
4
GND
1,8
5,8
8
1,8
5,8
MOUNTING HEIGHT CODES
CODE
A
B
C
HEIGHT (MAX)
0.187
0.240
0.290
DIP
Yes
Yes
Yes
SMD
No
Yes
Yes
Notes: T
I
represents nominal tap-to-tap delay increment
Tolerance on T
D
=
鹵
5% or
鹵
2ns, whichever is greater
Tolerance on T
I
=
鹵
5% or
鹵
1ns, whichever is greater
鈥淣/A鈥?indicates that delay is not available at this Z
Note:
Codes A and B are not available
for all values of T
D
Contact technical staff for details
漏
1997 Data Delay Devices
Doc #97029
2/7/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
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