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14081 Datasheet

  • 14081

  • B-Suffix Series CMOS Gates

  • 11頁(yè)

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
B-Suffix Series CMOS Gates
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
鈥?/div>
Supply Voltage Range = 3.0 Vdc to 18 Vdc
鈥?/div>
All Outputs Buffered
鈥?/div>
Capable of Driving Two Low鈥損ower TTL Loads or One Low鈥損ower
Schottky TTL Load Over the Rated Temperature Range.
鈥?/div>
Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
鈥?/div>
Pin鈥揻or鈥揚(yáng)in Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)
Quad 2-Input NOR Gate
Dual 4-Input NOR Gate
Quad 2-Input NAND Gate
Dual 4-Input NAND Gate
Triple 3-Input NAND Gate
Triple 3-Input NOR Gate
8-Input NAND Gate
Quad 2-Input OR Gate
Dual 4-Input OR Gate
Triple 3-Input AND Gate
Triple 3-Input OR Gate
8-Input NOR Gate
Quad 2-Input AND Gate
Dual 4-Input AND Gate
MC14001B
MC14002B
MC14011B
MC14012B
MC14023B
MC14025B
MC14068B
MC14071B
MC14072B
MC14073B
MC14075B
MC14078B
MC14081B
MC14082B
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
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TA = 鈥?55擄 to 125擄C for all packages.
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
V
V
鈥?0.5 to + 18.0
鹵
10
500
Vin, Vout
lin, lout
PD
Input or Output Voltage (DC or Transient)
鈥?0.5 to VDD + 0.5
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package鈥?/div>
Storage Temperature
mA
mW
Tstg
鈥?65 to + 150
_
C
TL
Lead Temperature (8鈥揝econd Soldering)
260
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
鈥燭emperature Derating:
Plastic 鈥淧 and D/DW鈥?Packages: 鈥?7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic 鈥淟鈥?Packages: 鈥?12 mW/
_
C From 100
_
C To 125
_
C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS
鈮?/div>
(Vin or Vout)
鈮?/div>
VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
漏
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14001B
7

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