10KE Datasheet

IC型號(hào)：
10KE
PDF描述：
Embedded Programmable Logic Device
文件大?。?/label>
1406.73KB
PDF頁數(shù)：
100頁
芯片廠家：
ALTERA

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FLEX 10KE

廬

Embedded Programmable

Logic Device

Data Sheet

January 2003, ver. 2.5

Features...

鈻?/div>

Embedded programmable logic devices (PLDs), providing

system-on-a-programmable-chip (SOPC) integration in a single

device

鈥?/div>

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

鈥?/div>

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

鈥?/div>

Logic array for general logic functions

High density

鈥?/div>

30,000 to 200,000 typical gates (see

Tables 1

and

鈥?/div>

Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be

used without reducing logic capacity

System-level features

鈥?/div>

MultiVolt

I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

鈥?/div>

Low power consumption

鈥?/div>

Bidirectional I/O performance (t

and

) up to 212 MHz

鈥?/div>

Fully compliant with the PCI Special Interest Group (PCI SIG)

PCI Local Bus Specification, Revision 2.2

for 3.3-V operation at

33 MHz or 66 MHz

鈥?/div>

-1 speed grade devices are compliant with

PCI Local Bus

Specification, Revision 2.2,

for 5.0-V operation

鈥?/div>

Built-in Joint Test Action Group (JTAG) boundary-scan test

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available

without consuming additional device logic

For information on 5.0-V FLEX

廬

10K or 3.3-V FLEX 10KA devices, see the

FLEX 10K Embedded Programmable Logic Family Data Sheet.

Table 1. FLEX 10KE Device Features

Feature

Typical gates

(1)

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

Maximum user I/O pins

Altera Corporation

DS-F10KE-2.5

EPF10K30E

30,000

119,000

1,728

24,576

220

EPF10K50E

EPF10K50S

50,000

199,000

2,880

40,960

254

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