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100331F Datasheet

  • 100331F

  • Low Power Triple D Flip-Flop

  • 8頁

  • NSC

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100331 Low Power Triple D Flip-Flop
August 1998
100331
Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
C
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
), Direct
Set (SD
n
) and Direct Clear (CD
n
) inputs. Data enters a mas-
ter when both CP
n
and CP
C
are LOW and transfers to a
slave when CP
n
or CP
C
(or both) go HIGH. The Master Set,
Master Reset and individual CD
n
and SD
n
inputs override
the Clock inputs. All inputs have 50 k鈩?pull-down resistors.
Features
n
n
n
n
n
n
35% power reduction of the 100131
2000V ESD protection
Pin/function compatible with 100131
Voltage compensated operating range = 鈭?.2V to 鈭?.7V
Available to industrial grade temperature range
Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Logic Symbol
Pin Names
CP
0
鈥揅P
2
CP
C
D
0
鈥揇
2
CD
0
鈥揅D
2
SD
n
MR
MS
Q
0
-Q
2
Q
0
鈥換
2
DS100300-1
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100300-3
DS100300-2
漏 1998 National Semiconductor Corporation
DS100300
www.national.com

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