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100315F Datasheet

  • 100315F

  • Low-Skew Quad Clock Driver

  • 6頁(yè)

  • NSC

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100315 Low-Skew Quad Clock Driver
August 1998
100315
Low-Skew Quad Clock Driver
General Description
The 100315 contains four low skew differential drivers, de-
signed for generation of multiple, minimum skew differential
clocks from a single differential input. This device also has
the capability to select a secondary single-ended clock
source for use in lower frequency system level testing. The
100315 is a 300 Series redesign of the 100115 clock driver.
n
n
n
n
n
Differential inputs and outputs
Secondary clock available for system level testing
2000V ESD protection
Voltage compensated operating range: 鈭?.2V to 鈭?.7V
Standard Microcircuit Drawing
(SMD) 5962-9469601
Features
n
Low output to output skew (鈮?0 ps)
Logic Diagram
DS100319-1
Connection Diagram
Flatpak
Pin Names
CLKIN, CLKIN
CLK
1鈥?
, CLK
1鈥?
TCLK
CLKSEL
Description
Differential Clock Inputs
Differential Clock Outputs
Test Clock Input (Note 1)
Clock Input Select (Note 1)
Note 1:
TCLK and CLKSEL are single-ended inputs, with internal 50 k鈩?pull-
down resistors.
DS100319-2
Truth Table
CLKSEL
L
L
H
H
CLKIN
L
H
X
X
CLKIN
H
L
X
X
TCLK
X
X
L
H
CLK
N
L
H
L
H
CLK
N
H
L
H
L
L = Low Voltage Level
H = High Voltage Level
X = Don鈥檛 Care
漏 1998 National Semiconductor Corporation
DS100319
www.national.com

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