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TVS Diode Application Note
PROTECTION PRODUCTS
10/100 ETHERNET PROTECTION
10/100 Ethernet ICs are vulnerable to damage from
electrostatic discharge (ESD). The fatal discharge may
originate from a charged cable or a 鈥渉uman body鈥?
Furthermore, devices used in telecommunications
equipment may be exposed to lightning induced tran-
sients. This application note illustrates a protection
circuit suitable for use in 10/100 Ethernet applica-
tions.
The original 10Base-T Ethernet chips were fairly large
geometry CMOS products that were not very sensitive
to static over-voltage. Newer 10/100 Ethernet de-
vices however have become extremely sensitive to
latch-up or damage as IC manufacturers have moved
to 0.35-micron and smaller line widths. These small
geometries are sensitive to fatal electrostatic dis-
charges that may originate from a charged cable,
lightning or a 鈥渉uman body鈥?
One of the most common electrostatic discharges is a
Cable Discharge Event (CDE). An Ethernet cable can
store up energy that will discharge into the circuit when
the cable is plugged into the connector causing a CDE.
Another frequent phenomenon is human thumbing of
the connectors of the cable. This charges each of the
connections that will discharge into the circuit upon
contact. Lightning can also induce high voltage onto
the lines that can be transferred to the protected IC.
Discharge from any source into the Ethernet interface
will charge the secondary windings of its transformer.
Once the surge is removed, the secondary winding will
stop charging and will transfer its stored energy to the
primary side where the protected IC sits. The internal
protection in the PHY chip, if any, often is not enough
due to the high energy of the discharges. If the dis-
charge is catastrophic, it will destroy the protected IC.
If it is less severe, it will cause latent failures that are
very difficult to find.
10/100 Ethernet operates at 125MHz clock over a
twisted pair interface. In a typical system, the twisted-
pair interface for each port consists of two differential
signal pairs: one for the transmitter and one for the
receiver, with the transmitter input being the most
sensitive to damage. The fatal discharge occurs
differentially across the transmit or receive line pair
and is capacitively coupled through the transformer to
Revision 09/14/2001
SI01-17
the Ethernet chip. The challenge is to find a TVS
(transient voltage suppressor) that will clamp low
enough as to prevent latch-up or damage to the
Ethernet IC. Also, the protection device must add
minimal loading capacitance as high parasitic capaci-
tance can cause significant degradation to the
100Mbps signal.
Semtech鈥檚 SRV05-4 meets all these criteria. The
circuit diagram of SRV05-4 is shown in Figure 1. It is
in a SOT-23 6L package and may be used to protect
two high-speed line pairs. The SRV05-4 combines
performance with proprietary process technology to
produce a low clamping voltage and capacitance
(typically 3pF line-to-ground and 1pF line-to-line) device
at an operating voltage of 5V. The 8kV contact ESD
response of the SRV05-4 can be seen in Figure 2.
Figure 3 shows the capacitance verse reverse voltage
curve. A plot of the SRV05-4 insertion loss from 3kHz
to 3GHz is shown in Figure 4. An eye pattern of the
SRV05-4 operating at 125MHz is shown in Figure 5 in
a line-to-ground configuration and in Figure 6 in a line-
to-line configuration. Figure 2 through 6 shows that
the SRV05-4 will maintain the Ethernet signal integrity
without attenuation. It also offers superior protection
to meet IEC 61000-4-2 level 4 (ESD 鈥?15kV air and
8kV contact), IEC 61000-4-4, level 4 EFT and IEC
61000-4-5 16A (8 x 20碌s) lightning surge.
SRV05-4
Figure 1 - SRV05-4 Schematic and Pin Configuration
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