Active and Passive Devices
出處：yuhh 發(fā)布于：2007-04-29 10:23:37
Active devices for R.F. include GaAs FETs, silicon bipolars and NMOS and possibly PMOS transistors. Standard library types for a given process vendor can usually be adapted to the requirement, and are strongly advocated to avoid layout errors.
Passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in GaAs circuits, but less so in silicon because the losses are greater.
Some sample device layouts are shown below:
Fig 2 : NMOS transistor, designed to a 2 lambda rule set, for 0.8 micron process
半導(dǎo)體技術(shù)天地[Semiconductor%20Technology%20World]芯片設(shè)計(jì)版圖工藝制程封裝測(cè)試wafer,chip,ic,process,layout,package,FA.files/3_AhHi0xo4XK70.jpg" onload="if(this.width>screen.width*0.7) {this.resized=true; this.width=screen.width*0.7; this.alt='Click here to open new window';}" border=0 onclick="if(this.resized) {window.open('https://ocean.bbs.topzj.com/attachments/m15//17/08/17083/forumid_22606/3_AhHi0xo4XK70.jpg');}">
One feature of many layout editors is the use of a 'lambda;' based rule set. The designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. Then, at a given process foundry, this rule may be interpreted as required. For example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. This is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.
Fig 3 : PMOS transistor
體</u></a>技術(shù)天地[Semiconductor%20Technology%20World]芯片<u>設(shè)計(jì)</u></a>版圖<u>工藝</u></a>制程<u>封裝</u></a><u>測(cè)試</u></a>wafer,chip,ic,process,layout,package,FA.files/4_L4YsUk2HJRMF.jpg)
Similarly, a PMOS device is shown above. In this case, the device is surrounded by an N-well, for correct polarity of conductors and isolation.
Fig 4 : Vertical NPN transistor
體</u></a>技術(shù)天地[Semiconductor%20Technology%20World]芯片<u>設(shè)計(jì)</u></a>版圖<u>工藝</u></a>制程<u>封裝</u></a><u>測(cè)試</u></a>wafer,chip,ic,process,layout,package,FA.files/5_OwZwtOLac7d4.jpg)
A more complex structure, not always available on MOS processes, is a vertical NPN bipolar transistor, as above. Again, a recommended layout from the process vendor should be used in this instance if possible.
Fig 5, Lateral PNP
體</u></a>技術(shù)天地[Semiconductor%20Technology%20World]芯片<u>設(shè)計(jì)</u></a>版圖<u>工藝</u></a>制程<u>封裝</u></a><u>測(cè)試</u></a>wafer,chip,ic,process,layout,package,FA.files/6_Y3bcpQ8a2pCF.jpg)
Less good, especially in the R.F. context, is the lateral PNP shown above. PNPs in general have not been well used in R.F. circuits, but new processes offer Fts close to those expected from the NPNs, so interesting circuits might be made in this respect.
Fig 6 : Polysilicon resistor
體</u></a>技術(shù)天地[Semiconductor%20Technology%20World]芯片<u>設(shè)計(jì)</u></a>版圖<u>工藝</u></a>制程<u>封裝</u></a><u>測(cè)試</u></a>wafer,chip,ic,process,layout,package,FA.files/7_3DyMbQqoRZgT.jpg)
For R.F. applications, polysilicon resistors are preferred, since they are deposited above the first oxide layers, and therefore have less capacitance to ground and other nodes than a similar value junction resistor. This ensures low parasitic capacitance. They are also voltage insensitive, although the temperature coefficient can be quite high, and should be carefully calculated, especially for the high sheet resistivities, which often have a negative coefficient.
Fig 7 : Poly1 - Poly2 capacitor
Capa體</u></a>技術(shù)天地[Semiconductor%20Technology%20World]芯片<u>設(shè)計(jì)</u></a>版圖<u>工藝</u></a>制程<u>封裝</u></a><u>測(cè)試</u></a>wafer,chip,ic,process,layout,package,FA.files/8_pdCC2VQoBKeB.jpg)
citors formed between the poly silicon layers ( Poly1 - poly2) are also preferred for R.F. applications. The reasoning is similar to that for the resistors. A rough rule is that the capacitance to ground from the bottom plate of the capacitor should be about 1/10 of the plate capacitance. Alternative sandwich capacitors such as metal to metal are usually poorer in this respect, although series resistance in the ploy1-poly2 type is an issue to be addressed.
Fig 8 : Inductor Layout
An inductor is the most difficult compromise in layout, and many papers have been written on this subject. The inductor above has some of the desirable features. These are:-
1. The centre is relatively open. Small turns add little inductance, just resistance and capacitance.
2. The turns are closely spaced, for minimum overall size. It may be improved by:-
3. Chamfered corners, although this is debated.
4. M2 instead of M1, because M2 is usually thicker and therefore lower resistance. M2 is alos lower capacitance to substrate. M3, when available is often better. This layout is from a chip where the M1 - M2 comparison is the subject of an experiment.
5. Larger central hole, although this may compromise size.
Passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in GaAs circuits, but less so in silicon because the losses are greater.
Some sample device layouts are shown below:
Fig 2 : NMOS transistor, designed to a 2 lambda rule set, for 0.8 micron process
One feature of many layout editors is the use of a 'lambda;' based rule set. The designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. Then, at a given process foundry, this rule may be interpreted as required. For example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. This is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.
Fig 3 : PMOS transistor
Similarly, a PMOS device is shown above. In this case, the device is surrounded by an N-well, for correct polarity of conductors and isolation.
Fig 4 : Vertical NPN transistor
A more complex structure, not always available on MOS processes, is a vertical NPN bipolar transistor, as above. Again, a recommended layout from the process vendor should be used in this instance if possible.
Fig 5, Lateral PNP
Less good, especially in the R.F. context, is the lateral PNP shown above. PNPs in general have not been well used in R.F. circuits, but new processes offer Fts close to those expected from the NPNs, so interesting circuits might be made in this respect.
Fig 6 : Polysilicon resistor
For R.F. applications, polysilicon resistors are preferred, since they are deposited above the first oxide layers, and therefore have less capacitance to ground and other nodes than a similar value junction resistor. This ensures low parasitic capacitance. They are also voltage insensitive, although the temperature coefficient can be quite high, and should be carefully calculated, especially for the high sheet resistivities, which often have a negative coefficient.
Fig 7 : Poly1 - Poly2 capacitor
Capa
citors formed between the poly silicon layers ( Poly1 - poly2) are also preferred for R.F. applications. The reasoning is similar to that for the resistors. A rough rule is that the capacitance to ground from the bottom plate of the capacitor should be about 1/10 of the plate capacitance. Alternative sandwich capacitors such as metal to metal are usually poorer in this respect, although series resistance in the ploy1-poly2 type is an issue to be addressed. Fig 8 : Inductor Layout
An inductor is the most difficult compromise in layout, and many papers have been written on this subject. The inductor above has some of the desirable features. These are:-
1. The centre is relatively open. Small turns add little inductance, just resistance and capacitance.
2. The turns are closely spaced, for minimum overall size. It may be improved by:-
3. Chamfered corners, although this is debated.
4. M2 instead of M1, because M2 is usually thicker and therefore lower resistance. M2 is alos lower capacitance to substrate. M3, when available is often better. This layout is from a chip where the M1 - M2 comparison is the subject of an experiment.
5. Larger central hole, although this may compromise size.
關(guān)鍵詞：Active and Passive Devices
版權(quán)與免責(zé)聲明
凡本網(wǎng)注明“出處：維庫(kù)電子市場(chǎng)網(wǎng)”的所有作品，版權(quán)均屬于維庫(kù)電子市場(chǎng)網(wǎng)，轉(zhuǎn)載請(qǐng)必須注明維庫(kù)電子市場(chǎng)網(wǎng)，http://m.58mhw.cn，違反者本網(wǎng)將追究相關(guān)法律責(zé)任。
本網(wǎng)轉(zhuǎn)載并注明自其它出處的作品，目的在于傳遞更多信息，并不代表本網(wǎng)贊同其觀點(diǎn)或證實(shí)其內(nèi)容的真實(shí)性，不承擔(dān)此類作品侵權(quán)行為的直接責(zé)任及連帶責(zé)任。其他媒體、網(wǎng)站或個(gè)人從本網(wǎng)轉(zhuǎn)載時(shí)，必須保留本網(wǎng)注明的作品出處，并自負(fù)版權(quán)等法律責(zé)任。
如涉及作品內(nèi)容、版權(quán)等問(wèn)題，請(qǐng)?jiān)谧髌钒l(fā)表之日起一周內(nèi)與本網(wǎng)聯(lián)系，否則視為放棄相關(guān)權(quán)利。
相關(guān)技術(shù)資料
- 什么是氫氧燃料電池,氫氧燃料電池的知識(shí)介紹2025/8/29 16:58:56
- SQL核心知識(shí)點(diǎn)總結(jié)2025/8/11 16:51:36
- 等電位端子箱是什么_等電位端子箱的作用2025/8/1 11:36:41
- 基于PID控制和重復(fù)控制的復(fù)合控制策略2025/7/29 16:58:24
- 什么是樹(shù)莓派?一文快速了解樹(shù)莓派基礎(chǔ)知識(shí)2025/6/18 16:30:52
技術(shù)分類
廣告
熱門技術(shù)資料
