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請(qǐng)求高手看看下面程序有什么問(wèn)題？非常感謝 |
| 作者：liuzsfly 欄目：通信技術(shù) |
使用的CPLD是XC95216-10，功能仿真和時(shí)序仿真都沒(méi)有問(wèn)題，但是實(shí)際下載以后，電路出現(xiàn)不穩(wěn)定現(xiàn)象，VHDL高手能不能幫我優(yōu)化一下程序，謝謝了！ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity GeneratePluse is PORT ( clkin: in std_logic; -- 10M clock PULSE: in std_logic; -- PULSE in 1K; reset: in std_logic; PULSEout1: out std_logic; -- 10us PULSE-width PULSEout1r: out std_logic; PULSEout2: out std_logic; -- 20us PULSE-width PULSEout2r: out std_logic; PULSEout3: out std_logic; -- 10.8us PULSE-width PULSEout3r: out std_logic ); end GeneratePluse; architecture Behavioral of GeneratePluse is signal cf: std_logic; signal counter_a: std_logic_vector(13 downto 0); signal counter_b: std_logic_vector(13 downto 0); signal counter_c: std_logic_vector(13 downto 0); begin PROCESS(reset,PULSE) begin if reset = '0' then cf <= '0'; elsif falling_edge(PULSE) then cf <= not cf; end if; end PROCESS; PROCESS(clkin,cf) begin if rising_edge(clkin) then if cf='1' then counter_a <= counter_a + 1; counter_b <= (others => '0'); else counter_b <= counter_b + 1; counter_a <= (others => '0'); end if; end if; end PROCESS; PROCESS(PULSE) begin if rising_edge(PULSE) then if cf='1' then counter_c <= counter_a; else counter_c <= counter_b; end if; end if; end PROCESS; PROCESS(clkin) begin if falling_edge(clkin) then PULSEout1 <= PULSE; PULSEout1r <= not PULSE; end if; end PROCESS; PROCESS(clkin,cf,counter_a,counter_b) begin if falling_edge(clkin) then if cf='1' then if counter_a > counter_c - 100 then PULSEout2 <= '1'; PULSEout2r<= '0'; else PULSEout2 <= '0'; PULSEout2r<= '1'; end if; else if counter_b > counter_c - 100 then PULSEout2 <= '1'; PULSEout2r<= '0'; else PULSEout2 <= '0'; PULSEout2r<= '1'; end if; end if; end if; end PROCESS; PROCESS(clkin,cf,counter_a,counter_b) begin if falling_edge(clkin) then if cf='1' then if counter_a <5 or counter_a > counter_c - 3 then PULSEout3 <= '1'; PULSEout3r<= '0'; else PULSEout3 <= '0'; PULSEout3r<= '1'; end if; else if counter_b < 5 or counter_b > counter_c - 3 then PULSEout3 <= '1'; PULSEout3r<= '0'; else PULSEout3 <= '0'; PULSEout3r<= '1'; end if; end if; end if; end PROCESS; end Behavioral; |
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