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一個(gè)簡(jiǎn)單時(shí)序電路的VHDL語(yǔ)言求助！��！ |
| 作者：liuzsfly 欄目：數(shù)字廣電 |
信號(hào)輸入：周期脈沖信號(hào)b（周期信號(hào)，周期在1K到2K變化），5伏TTL電平 輸出信號(hào)：周期脈沖信號(hào)a，b，c；滿足下面時(shí)序關(guān)系，電平是5伏TTL電平 圖1 信號(hào)時(shí)序圖 我的解決思路是選用XILINX公司的XC9500系列的CPLD實(shí)現(xiàn)，外加一個(gè)20M時(shí)鐘信號(hào)，用VHDL寫了一個(gè)程序，功能仿真沒(méi)有問(wèn)題，但是后仿真出現(xiàn)了毛刺，沒(méi)有什么好的解決辦法，請(qǐng)高手幫忙看看我的程序有什么問(wèn)題沒(méi)有？順便問(wèn)一下除了XC9500系列外，還有沒(méi)有5V標(biāo)準(zhǔn)性能好一點(diǎn)的CPLD或FPGA芯片？ 程序如下： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating XILINX primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity Plusetime is PORT ( clkin: in std_logic; -- 20M clock PULSE: in std_logic; -- PULSE in 1K; reset: in std_logic; PULSEout1: out std_logic; -- 10us PULSE-width PULSEout1r: out std_logic; PULSEout2: out std_logic; -- 20us PULSE-width PULSEout2r: out std_logic; PULSEout3: out std_logic; -- 11us PULSE-width PULSEout3r: out std_logic --counterc: out std_logic_vector(15 downto 0); --counter: out std_logic_vector(15 downto 0) ); end Plusetime; architecture Behavioral of Plusetime is signal cf: std_logic; signal counter_a: std_logic_vector(15 downto 0); signal counter_b: std_logic_vector(15 downto 0); signal counter_c: std_logic_vector(15 downto 0); begin PROCESS(reset,PULSE) begin if reset = '1' then cf <= '0'; elsif falling_edge(PULSE) then cf <= not cf; end if; end PROCESS; PROCESS(clkin,cf) begin if rising_edge(clkin) then if cf='1' then counter_a <= counter_a + 1; counter_b <= (others => '0'); else counter_b <= counter_b + 1; counter_a <= (others => '0'); end if; end if; end PROCESS; PROCESS(PULSE) begin if rising_edge(PULSE) then if cf='1' then counter_c <= counter_a; else counter_c <= counter_b; end if; end if; end PROCESS; PROCESS(clkin) begin if falling_edge(clkin) then PULSEout1 <= PULSE; PULSEout1r <= not PULSE; end if; end PROCESS; PROCESS(clkin,cf,counter_a,counter_b) begin if falling_edge(clkin) then if cf='1' then if counter_a > counter_c - 200 then PULSEout2 <= '1'; PULSEout2r<= '0'; else PULSEout2 <= '0'; PULSEout2r<= '1'; end if; else if counter_b > counter_c - 200 then PULSEout2 <= '1'; PULSEout2r<= '0'; else PULSEout2 <= '0'; PULSEout2r<= '1'; end if; end if; end if; end PROCESS; PROCESS(clkin,cf,counter_a,counter_b) begin if falling_edge(clkin) then if cf='1' then if counter_a <10 or counter_a > counter_c - 6 then PULSEout3 <= '1'; PULSEout3r<= '0'; else PULSEout3 <= '0'; PULSEout3r<= '1'; end if; else if counter_b <10 or counter_b > counter_c - 6 then PULSEout3 <= '1'; PULSEout3r<= '0'; else PULSEout3 <= '0'; PULSEout3r<= '1'; end if; end if; end if; end PROCESS; --cfout <= cf; --counterc <= counter_c; --counter <= counter_a; end Behavioral; |
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