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幫忙看看代碼，為什么PIC16F72的T1不能產生溢出中斷？ |
| 作者：lqn168 欄目：單片機 |
#define D_PS 5 //預分頻: 32 #define D_PSA 1 //1 = Prescaler is assigned to the WDT #define D_T0SE 0 //0 = Increment on low-to-high transition on RA4/T0CKI pin #define D_T0CS 0 //0 = Internal instruction cycle clock (CLKOUT) #define D_INTEDG 0 //0 = Interrupt on falling edge of RB0/INT pin #define D_RBPU 0 //0:PB上拉便能 #define D_OPTION (D_PS | D_PSA<<3 | D_T0SE<<4 | D_T0CS<<5 | D_INTEDG<<6 | D_RBPU<<7) // #define D_T1CKPS 0 //預分頻 :0 #define D_T1OSCEN 0 //0 = Oscillator is shut off #define D_T1SYNC 1 //This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. #define D_TMR1CS 0 //0 = Internal clock (FOSC/4) #define D_TTMR1ON 1 //1 = Enables Timer1 #define D_T1CON (D_T1CKPS<<4 | D_T1OSCEN<<3 | D_T1SYNC<<2 | D_TMR1CS<<1 | D_TTMR1ON) // main() { OPTION = D_OPTION; T1CON = D_T1CON; GIE = 1; TMR1IE = 1; TMR1L = (Int08u)((Int16u)58845%256); TMR1H = (Int08u)((Int16u)58845/256); while(1); } void interrupt Int_isr(void) { //定時器1溢出 if (TMR1IF) { TMR1IF = 0; TMR1L = (Int08u)((Int16u)58845%256); TMR1H = (Int08u)((Int16u)58845/256); } } |
| 2樓： | >>參與討論 |
| 作者： maoqichun 于 2006/2/17 11:00:00 發(fā)布：
1.你的頭文件可能選擇不對 2.將TMR1IE改為PEIE |
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| 3樓： | >>參與討論 |
| 作者： lqn168 于 2006/2/17 11:18:00 發(fā)布：
TMR1IE是8ch.0沒有錯 /* * HEADER file for the MICROCHIP * PIC 16F72 chip * PIC 16F73 chip * PIC 16F74 chip * PIC 16F76 chip * PIC 16F77 chip * Midrange Microcontroller */ #if defined(_16F74) || defined(_16F77) #define __PINS_40 #endif static volatile unsigned CHAR TMR0 @ 0x01; static volatile unsigned CHAR PCL @ 0x02; static volatile unsigned CHAR STATUS @ 0x03; static unsigned CHAR FSR @ 0x04; static volatile unsigned CHAR PORTA @ 0x05; static volatile unsigned CHAR PORTB @ 0x06; static volatile unsigned CHAR PORTC @ 0x07; #ifdef __PINS_40 static volatile unsigned CHAR PORTD @ 0x08; static volatile unsigned CHAR PORTE @ 0x09; #endif static unsigned CHAR PCLATH @ 0x0A; static volatile unsigned CHAR INTCON @ 0x0B; static volatile unsigned CHAR PIR1 @ 0x0C; #ifndef _16F72 static volatile unsigned CHAR PIR2 @ 0x0D; #endif static volatile unsigned CHAR TMR1L @ 0x0E; static volatile unsigned CHAR TMR1H @ 0x0F; static volatile unsigned CHAR T1CON @ 0x10; static volatile unsigned CHAR TMR2 @ 0x11; static volatile unsigned CHAR T2CON @ 0x12; static volatile unsigned CHAR SSPBUF @ 0x13; static volatile unsigned CHAR SSPCON @ 0x14; static volatile unsigned CHAR CCPR1L @ 0x15; static volatile unsigned CHAR CCPR1H @ 0x16; static volatile unsigned CHAR CCP1CON @ 0x17; #ifndef _16F72 static volatile unsigned CHAR RCSTA @ 0x18; static volatile unsigned CHAR TXREG @ 0x19; static volatile unsigned CHAR RCREG @ 0x1A; static volatile unsigned CHAR CCPR2L @ 0x1B; static volatile unsigned CHAR CCPR2H @ 0x1C; static volatile unsigned CHAR CCP2CON @ 0x1D; static volatile unsigned CHAR ADRES @ 0x1E; #endif static volatile unsigned CHAR ADCON0 @ 0x1F; /* bank 1 registers */ static unsigned CHAR bank1 OPTION @ 0x81; static volatile unsigned CHAR bank1 TRISA @ 0x85; static volatile unsigned CHAR bank1 TRISB @ 0x86; static volatile unsigned CHAR bank1 TRISC @ 0x87; #ifdef __PINS_40 static volatile unsigned CHAR bank1 TRISD @ 0x88; static volatile unsigned CHAR bank1 TRISE @ 0x89; #endif static volatile unsigned CHAR bank1 PIE1 @ 0x8C; #ifndef _16F72 static volatile unsigned CHAR bank1 PIE2 @ 0x8D; #endif static volatile unsigned CHAR bank1 PCON @ 0x8E; static volatile unsigned CHAR bank1 PR2 @ 0x92; static volatile unsigned CHAR bank1 SSPADD @ 0x93; static volatile unsigned CHAR bank1 SSPSTAT @ 0x94; #ifndef _16F72 static volatile unsigned CHAR bank1 TXSTA @ 0x98; static volatile unsigned CHAR bank1 SPBRG @ 0x99; #endif static volatile unsigned CHAR bank1 ADCON1 @ 0x9F; /* bank 2 registers */ #ifdef _16F72 static volatile unsigned CHAR bank2 PMDATL @ 0x10C; static volatile unsigned CHAR bank2 PMADRL @ 0x10D; #else static volatile unsigned CHAR bank2 PMDATA @ 0x10C; static volatile unsigned CHAR bank2 PMADR @ 0x10D; #endif static volatile unsigned CHAR bank2 PMDATH @ 0x10E; static volatile unsigned CHAR bank2 PMADRH @ 0x10F; /* bank 3 registers */ static volatile unsigned CHAR bank3 PMCON1 @ 0x18C; /* STATUS bits */ static volatile bit IRP @ (unsigned)&STATUS*8+7; static volatile bit RP1 @ (unsigned)&STATUS*8+6; static volatile bit RP0 @ (unsigned)&STATUS*8+5; static volatile bit TO @ (unsigned)&STATUS*8+4; static volatile bit PD @ (unsigned)&STATUS*8+3; static volatile bit ZERO @ (unsigned)&STATUS*8+2; static volatile bit DC @ (unsigned)&STATUS*8+1; static volatile bit CARRY @ (unsigned)&STATUS*8+0; /* PORTA bits */ static volatile bit RA5 @ (unsigned)&PORTA*8+5; static volatile bit RA4 @ (unsigned)&PORTA*8+4; static volatile bit RA3 @ (unsigned)&PORTA*8+3; static volatile bit RA2 @ (unsigned)&PORTA*8+2; static volatile bit RA1 @ (unsigned)&PORTA*8+1; static volatile bit RA0 @ (unsigned)&PORTA*8+0; /* PORTB bits */ static volatile bit RB7 @ (unsigned)&PORTB*8+7; static volatile bit |
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| 4樓： | >>參與討論 |
| 作者： maoqichun 于 2006/2/17 12:53:00 發(fā)布：
是加入PEIE=1;已測試通過 |
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