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| 技術(shù)交流 | 電路欣賞 | 工控天地 | 數(shù)字廣電 | 通信技術(shù) | 電源技術(shù) | 測(cè)控之家 | EMC技術(shù) | ARM技術(shù) | EDA技術(shù) | PCB技術(shù) | 嵌入式系統(tǒng) 驅(qū)動(dòng)編程 | 集成電路 | 器件替換 | 模擬技術(shù) | 新手園地 | 單 片 機(jī) | DSP技術(shù) | MCU技術(shù) | IC 設(shè)計(jì) | IC 產(chǎn)業(yè) | CAN-bus/DeviceNe |
多端口低功耗智能16位微控器參數(shù) |
| 作者：luvkyhj 欄目：數(shù)字廣電 |
賽恩ECOG1X產(chǎn)品系列參數(shù) 0 to 75MHz 1.8V processor ♦ 3.3/5V tolerant I/O ♦ Powerful arithmetic operations ♦ Barrel Shifter ♦ Harvard Architecture ♦ 64Kx16 Data MEMORY Space ♦ 16Mx16 Program MEMORY Space ♦ Built in EMULATOR (eICE) ♦ Low POWER operation ♦ 512/256/128Kbytes FLASH EPROM ♦ 24/16/8Kbytes SRAM ♦ MMU ♦ Power-saving code cache ♦ Code security feature ♦ External Host Interface ♦ External MEMORY Interface ♦ FAST Vectored Interrupts ♦ 2 off DUARTs ♦ DUAL USART ♦ - SMART Card Interface ♦ - SPI ♦ - I2C ♦ - Infra-Red LINK SUPPORT ♦ I2S ♦ SPI ♦ DUAL 7 channel 12-bit ADCs ♦ DUAL 12-bit DACs ♦ Temperature Sensor ♦ Supply Voltage Sensor ♦ Power-On Reset ♦ USB 2.0 480Mbit On The Go ♦ 10/100 Ethernet MAC ♦ 4X32 LCD Controller ♦ 5 MULTI Purpose Timers ♦ Watchdog Timer ♦ LONG Interval Timer ♦ Clock Timer ♦ PWM timers ♦ PWM motor CONTROL ♦ Parallel Interface ♦ 136 General Purpose I/O pins ♦ Low POWER relaxation oscillator ♦ Interfaces to 8/16/32-bit CPU Core • 16-bit 75MHz core. • Harvard architecture. • SUPPORTs a full array of 16-bit arithmetic operations, including both signed and unsigned MULtiply and DIVide instructions. • 32MByte LINEAR program MEMORY. • 128KByte LINEAR data MEMORY. • Vectored interrupts. • Full ICE debug SUPPORT. MMU • Performs logical to physical address translations. • Translates between RAM, Program MEMORY, and external MEMORY DEVICEs for both code and data accesses concurrently. • Lookup tables in RAM or FLASH can be mapped between each MEMORY area. • Up to 4 concurrent translations to external DEVICEs from code addresses. • Up to 4 concurrent translations to external DEVICEs from data addresses. • Programmable wait state generation. • Concurrent accesses to same DEVICE are prioritised. • Translations are prioritised to allow overlapped translations. FLASH MEMORY • 512/256/128Kbytes, 16 bits wide. • Organised into multiple sectors. • Can be mapped into both code and data spaces. • Individual FLASH sectors can be read and/or write protected. • Simple PROGRAMMING via JTAG interface, with eICE SUPPORT for PROGRAMMING for user access. Code Cache • Individual cache entries can be locked. • Can cache both User and Interrupt Mode. Static RAM • 24/16/8Kbytes, 16 bits wide. • Can be mapped into both code and data spaces. External MEMORY Interface • 8 or 16-bit data bus. • 16 or 24-bit address bus. • MULTIplexed address/data for 16-bit data bus. • External DEVICEs can be mapped into both code and data space. • SUPPORTs SRAM (bus) and SDRAM interface modes. • SUPPORTs up to 128M SINGLE Data Rate 16-bit wide SDRAMs. • Four Row/Column SDRAM address multiplexing schemes. • SUPPORTs SDRAM auto and self refresh. • Configurable timing. • SUPPORTs low POWER SDRAM suspend/standby mode. • SINGLE cycle data space access, code space burst access in conjunction with Code Cache. • HARDWARE SUPPORT for SOFTWARE initialisation and refresh of SDRAM. External Host Interface (EHI) • Provides an interface to an external host processor or FIFO. • SUPPORTs both DMA and MEMORY mapped peripheral modes. • Interrupt generated upon transfer. DMA Mode: • SUPPORTs MASTER and slave mode timings. • 16/32-bit data bus. • Request & Acknowledge CONTROL LINEs. • Configurable MASTER mode timing. • DMA connection into internal SRAM (11-bit block address, max 256 byte block size). • Internal DMA CONTROLler SUPPORTs circular and linked list buffer models. MEMORY Mapped Mode: • Selectable block size 256 x 16-bit data 8 x 32-bit data. • Three CONTROL LINEs: chip SELECT, read/write direction and wait. • Configurable CONTROL LINE senses. DUART (2 off) • Each DUART has two independent RS232 compatible asynchronous double-buffered serial ports. • SUPPORTing 5, 6, 7, or 8-bits of data • 1, 1.5, or 2 stop bits. • Even, odd or no parity. • Automatic end-of-frame guard time insertion of 0- to 64-bit periods. • Receive time-out detection 0 to 64-bit periods. • SOFTWARE LINE Break generation. • Programmable Baud rate generator. • Interrupts generated on full and empty. • RECEIVER error detection for false start bits, parity errors and frame errors. • Configurable data polarity. • Over-sampling of received data for noise immunity. DUSART • Two synchronous/asynchronous double-buffered serial ports. • Programmable baud rate generator. • End of frame guard time insertion of 0 to 64-bit periods. • Receive time-out detection 0 to 64-bit periods. • RECEIVER error detection for false Start bits, Parity errors, Frame errors and Buffer overflow. • Configurable data and clock polarity. • Configurable data packing, MSB or LSB first. • Over sampling of receive data for noise immunity. Asynchronous Interface: • Asynchronous frames SUPPORTing 5, 6, 7, or 8-bits of data. • 1, 1.5, or 2 stop bits. • Even, odd or no parity. • Full MODEM SUPPORT using GPIO. • SOFTWARE LINE Break generation. Synchronous Interface: • Local or external transmit and receive clock. • Full or half duplex. • Frame sizes from 1 to 16-bits with larger frames possible. • SUPPORT for NRZ, RZ. • PM, PWM and ASK modulation if used in conjunction with PWM timer. I2C: • Two wire I2C compatible port. • Address matching. • ACK bit and wait state insertion. • MULTI-MASTER arbitration. • SUPPORTs 10-bit addressing and FAST mode. SPI: • MULTI-slave SPI SYSTEM. • Four slave SELECT LINEs. • Both MASTER and slave roles. • Programmable serial clock polarity and phase. • SUPPORT for high speed directly clocked operation and sampled filtered operation. SMART Card Interface: • ISO 7816 compatible SMART card interface. • MULTIprocessor SUPPORT. • Byte level SUPPORT for T=0 and T=1 transmission protocols. • Detection and generation of the transmission error signal for T=0 protocol. • Automatic retransmissi |
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