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問一個VHDL的錯誤提示信息 |
| 作者:zxchit 欄目:技術(shù)交流 |
signal "XXX" has multiple sources. 這個錯誤提示的原因是什么呀?找了一個下午都沒找到。源程序如下。為一個可預置的24位可逆計數(shù)器。"sig"為輸出的計數(shù)符號給單片機。錯誤提示有四條,類型都是上面的同一個。XXX代表程序中的四個信號:q,sig,tmp,tmp_sig.請各位有時間掃兩眼,幫忙看一下。多謝了! LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; ENTITY counter IS PORT( PULSE,up_down,reset,load,load_sig :IN STD_LOGIC; unit_sel: IN STD_LOGIC_VECTOR(1 downto 0); q : IN STD_LOGIC_VECTOR(7 downto 0); sig : out std_logic; d : out STD_LOGIC_VECTOR(23 downto 0) ); END counter; ARCHITECTURE counter_arch OF counter IS SIGNAL dir :STD_LOGIC; signal tmp_sig :std_logic; signal tmp :STD_LOGIC_VECTOR(23 downto 0); BEGIN load_reset:PROCESS.html">PROCESS (reset,load,unit_sel) begin if reset='0' then tmp<="000000000000000000000000"; tmp_sig<=load_sig; elsif(load'event)and(load='1')then case unit_sel is when "00" => tmp(23 downto 16)<=q; when "01"=> tmp(15 downto 8)<=q; when others => tmp(7 downto 0)<=q; end case; end if; d<=tmp; sig<=tmp_sig; end PROCESS.html">PROCESS load_reset; count:PROCESS (PULSE,up_down,tmp_sig,dir,tmp) BEGIN if (PULSE'event)and(PULSE='1') then if tmp="000000000000000000000000" then if(up_down='1')then tmp_sig<='1'; else tmp_sig<='0'; end if; end if; if (tmp_sig='1')then dir<=up_down; else dir<=not up_down; end if; if dir='1' then tmp<=tmp + 1; else tmp<=tmp - 1; end if; end if; d<=tmp; sig<=tmp_sig; END PROCESS count; END counter_arch; |
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