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很多朋友找POWERPC基本啟動(dòng)代碼，我編寫(xiě)的一段，是現(xiàn)代的SDRAM |
| 作者：xillinx 欄目：嵌入式系統(tǒng) |
#//***************************************************************************** #//* Load.s #//* This file contains the target processor dependent initialization #//* routines and data #//* Created By xillinx 2004-08-03 #//***************************************************************************** .file "Load.s" #//***************************************************************************** #//* Define constants used in low-level initialization. #//***************************************************************************** CACHE_DISABLE .equ 0x0400 #//* Command to disable cache CACHE_ENABLE .equ 0x0200 #//* Command to enable cache CACHE_UNLK_ALL .equ 0x0a00 #//* Command to unlock all cache entries CACHE_INV_ALL .equ 0x0c00 #//* Command to invalidate all entries #//***************************************************************************** #//* Define offsets of memory-mapped registers. All of these are offset #//* from the base address contained in the IMMR register #//***************************************************************************** SIUMCR .equ 0x000 #//* SIU MODULE CONTROL Register SYPCR .equ 0x004 #//* SIU SYSTEM Protection CONTROL SIVEC .equ 0x01c #//* SIU Interrupt Vector BR0 .equ 0x100 #//* Base Register 0 OR0 .equ 0x104 #//* Option Register 0 BR1 .equ 0x108 #//* Base Register 1 OR1 .equ 0x10C #//* Option Register 1 BR2 .equ 0x110 #//* Base Register 2 OR2 .equ 0x114 #//* Option Register 2 BR3 .equ 0x118 #//* Base Register 3 OR3 .equ 0x11C #//* Option Register 3 BR4 .equ 0x120 #//* Base Register 4 OR4 .equ 0x124 #//* Option Register 4 BR5 .equ 0x128 #//* Base Register 5 OR5 .equ 0x12C #//* Option Register 5 BR6 .equ 0x130 #//* Base Register 6 OR6 .equ 0x134 #//* Option Register 6 BR7 .equ 0x138 #//* Base Register 7 OR7 .equ 0x13C #//* Option Register 7 MAR .equ 0x164 #//* MEMORY Command MCR .equ 0x168 #//* MEMORY Command MAMR .equ 0x170 #//* Machine A Mode Register MBMR .equ 0x174 #//* Machine B Mode Register MPTPR .equ 0x17A #//* MEMORY Periodic Timer Prescaler MDR .equ 0x17C #//* MEMORY Data TBSCR .equ 0x200 #//* Time Base Status and CONTROL Register RTCSC .equ 0x220 #//* Real-time Clock Status and CONTROL PISCR .equ 0x240 #//* PIT Status and CONTROL PLPRCR .equ 0x284 #//* PLL CONTROL Register RTCSCK .equ 0x320 #//* Real-time Clock Status CONTROL Key CIVR .equ 0x930 #//* CP Interrupt Vector Register CICR .equ 0x940 #//* CP Interrupt Configuration Register CISR .equ 0x94C #//* CP In-Service Register SCCR .equ 0x280 #//* CP In-Service Register PBDIR .equ 0xAB8 #//* PB DIR PBPAR .equ 0xABC #//* PB PAR PBDAT .equ 0xAC4 #//* PB DAT BR0_H .equ 0xFFC0 #//* BR0 High Addr ISP_H .equ 0xFFF2 #//* ISP High Addr #//***************************************************************************** #//* Main PROCESS #//***************************************************************************** .section ".vectors",,x .align 2 INT_Vectors: .skip 0x0100-(.-INT_Vectors) # SYSTEM reset _start: li r0,0 #//*------------------------------------------------------------------------ #//* Disable data cache #//*------------------------------------------------------------------------ lis r3,CACHE_DISABLE mtspr DC_CST,r3 #//*------------------------------------------------------------------------ #//* Disable Instruction cache #//* chen hongwei for debug #//*------------------------------------------------------------------------ lis r3,CACHE_DISABLE mtspr IC_CST,r3 #//*------------------------------------------------------------------------ #//* Enable machine check exceptions and set RI bit #//*------------------------------------------------------------------------ lis r3,0x0 ori r3,r3,0x1002 mtmsr r3 #//*------------------------------------------------------------------------ #//* Set ICTRL = 7 to turn off show cycles #//*------------------------------------------------------------------------ lis r3,0x0000 ori r3,r3,0x0007 mtspr ICTRL,r3 &nb |
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