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程序?yàn)槭裁床荒苓M(jìn)中斷，附代碼，請大蝦指點(diǎn) |
| 作者：jdf 欄目：ARM技術(shù) |
系統(tǒng)配置4510B，FLASH.html">FLASH :2M 硬件鏈接ROMCON0 .SDRAM：8M 硬件鏈接SDRAMCON0 也就是一個ARM的最小系統(tǒng)。 程序沒有使用REMAP,中斷向量放在ROM中.程序的目的就是通過進(jìn)Timer0中斷進(jìn)行LED的閃爍。 程序如下: Vector.s ;;; COPYRIGHT ARM Ltd 2001. All rights reserved. AREA Vect, CODE, READONLY ; These are example exception vectors and exception handlers ; ; ***************** ; Exception Vectors ; ***************** ; Note: LDR PC instructions are used here, though branch (B) instructions ; could also be used, unless the ROM is at an address >32MB. ENTRY LDR PC, Reset_Addr LDR PC, Undefined_Addr LDR PC, SWI_Addr LDR PC, Prefetch_Addr LDR PC, Abort_Addr NOP ; Reserved vector LDR PC, IRQ_Addr LDR PC, FIQ_Addr IMPORT Reset_Handler ; In init.s IMPORT IRQ_Handler ; In main.c Reset_Addr DCD Reset_Handler Undefined_Addr DCD Undefined_Handler SWI_Addr DCD SWI_Handler Prefetch_Addr DCD Prefetch_Handler Abort_Addr DCD Abort_Handler IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ_Handler ; ************************ ; Exception Handlers ; ************************ ; The following DUMMY handlers do not do anything useful in this example. ; They are set up here for completeness. Undefined_Handler B Undefined_Handler SWI_Handler B SWI_Handler Prefetch_Handler B Prefetch_Handler Abort_Handler B Abort_Handler FIQ_Handler B FIQ_Handler END init.s: ;************************************************************** ; ; This an simple implementation of bootloader for S3C4510B ; Hope it is useful to you. ;************************************************************** LOOPNUM EQU 0x02 AREA Init, CODE, READONLY CODE32 GET snds.s ENTRY EXPORT Reset_Handler Reset_Handler ;PART 1 ;*************************************************************** ;disable interrupts in CPU and SWITCH to SVC32 mode MRS r0, cpsr BIC r0, r0, #MASK_MODE ORR r0, r0, #MODE_SVC32 ORR r0, r0, #I_BIT ORR r0, r0, #F_BIT MSR cpsr_c, r0 LDR r2, =ARM7_INTMASK ;R2->interrupt controller MVN r1, #0 ;&FFFFFFFF STR r1, [r2] ;disable all interrupt soucres LDR r2, =ARM7_INTPEND ;R2->interrupt pend register. MVN r1, #0 ;&FFFFFFFF STR r1, [r2] ;clear all interrupt flags. ;PART 2 ;**************************************************************** LDR r0, =ARM7_SYSCFG LDR r1, =0xE7ffffA0 ;config SYSCFG STR r1, [r0] ;Cache & WB disabled ;***************************************************************** ;**************************************************************** ;Initalize the MEMORY as followa: ; FLASH @ 0 ~ 2 M ; SDRAM @ 2 ~ 10M LDR r1, =rEXTDBWTH ;EXTDBWTH LDR r2, =rROMCON0 ;ROMCON0 @ 0M ~ 2M LDR r3, =rROMCON1 ;ROMCON1 @ DISABLED LDR r4, =rROMCON2 ;ROMCON1 @ DISABLED LDR r5, =rROMCON3 ;ROMCON1 @ DISABLED LDR r6, =rROMCON4 ;ROMCON1 @ DISABLED LDR r7, =rROMCON5 ;ROMCON1 @ DISABLED LDR r8, =rSDRAMCON0 ;SDRAMCON0 @ 2M ~ 10M LDR r9, =rSDRAMCON1 ;SDRAMCON1 @ DISABLED LDR r10,=rSDRAMCON2 ;SDRAMCON2 @ DISABLED LDR r11,=rSDRAMCON3 ;SDRAMCON3 @ DISABLED LDR r12,=rSREFEXTCON LDR r0, =ARM7_EXTDBWTH STMIA r0, {r1-r12} ;*************************************** ;set IRQ mode Stack ;*************************************** MRS r0, cpsr BIC r0, r0, #MASK_MODE ORR r0, r0, #Mode_IRQ ORR r0, r0, #I_BIT ORR r0, r0, #F_BIT MSR cpsr_c, r0 LDR r0, =ARM7_SYSCFG LDR r1,=0xE7FFFF80 STR r1,[r0] LDR SP,=0x3FE1000 LDR R7,=&0 ;r7作為標(biāo)志位 ;*************************************** ;set SVC mode ;*************************************** MRS r0, cpsr BIC r0, r0, #MASK_MODE ORR r0, r0, #MODE_SVC32 ORR r0, r0, #I_BIT ORR r0, r0, #F_BIT MSR cpsr_c, r0 ;**************************************** ; Initialize IO ;**************************************** ;********************************* ;LED DISPLAY ;********************************* LDR R1,=ARM7_IOPMOD LDR R0,=&ff STR R0,[R1] LDR R1,=ARM7_IOPDATA LDR R0,=&07 STR R0,[R1] EOR R0,R0,R0 LEDDELAY1 ADD R0,R0,#1 C |
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