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誰能告訴我錯在那兒如何改正
作者：xing198200　欄目：EDA技術(shù)
誰能告訴我錯在那兒如何改正
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY add_lp IS
GENERIC(WIDTH:INTEGER:=15;
         WIDTH1:INTEGER:=7;
         WIDTH2:INTEGER:=8;
         ONE   :INTEGER:=1);
PORT(x,y:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
      sum:OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
      clk:IN STD_LOGIC);
END add_lp;
ARCHITECTURE flex OF add_lp IS
SIGNAL l1,l2,r1,q1
                   :STD_LOGIC_VECTOR(WIDTH1-1 DOWNTO 0);
SIGNAL l3,l4,r2,q2,u2,h2
                   :STD_LOGIC_VECTOR(WIDTH2-1 DOWNTO 0);
SIGNAL s          :STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
SIGNAL crl,cql    :STD_LOGIC_VECTOR(ONE-1 DOWNTO 0);


BEGIN
   PROCESS
    BEGIN
      WAIT UNTIL clk='1';
      FOR k IN WIDTH1-1 DOWNTO 0 LOOP
        l1(k)<=x(k);
        l2(k)<=y(k);
      END LOOP;
      FOR k IN WIDTH2-1 DOWNTO 0 LOOP
         l3(k)<=x(k+WIDTH1);
          l4(k)<=y(k+WIDTH1);
      END LOOP;
   END PROCESS;
add_1:lpm_add_sub
       GENERIC MAP(LPM_WIDTH=>WIDTH1,
                   LPM_REPRESENTATION=>"UNSIGNED",
                    LPM_DIRECTION=>"ADD")
          PORT MAP(dataa=>l1,datab=>l2,
                    result=>r1,cout=>crl(0));
reg_1:lpm_ff
       GENERIC MAP(LPM_WIDTH=>WIDTH1)
        PORT MAP(data=>r1,q=>q1,clock=>clk);
reg_2:lpm_ff
        GENERIC MAP(LPM_WIDTH=>ONE)
        PORT MAP(data=>crl,q=>cql,clock=>clk);
add_2:lpm_add_sub
        GENERIC MAP(LPM_WIDTH=>WIDTH2,
                    LPM_REPRESENTATION=>"UnSIGNED",
                    LPM_DIRECTION=>"ADD")
         PORT MAP(dataa=>l3,datab=>l4,result=>r2);
reg_3:lpm_ff
         GENERIC MAP(LPM_WIDTH=>WIDTH2)
         PORT MAP(data=>r2,q=>q2,clock=>clk);

h2<=(OTHERS=>'0';
add_3:lpm_add_sub
      GENERIC MAP(LPM_WIDTH=>WIDTH2,
                    LPM_REPRESENTATION=>"UNSIGNED",
                    LPM_DIRECTION=>"ADD")
        PORT MAP(cin=>cql(0),data=>q2,
                  datab=>h2,result=>u2);
PROCESS
  BEGIN
   WAIT UNTIL clk='1';
  FOR k IN WIDTH1-1 DOWNTO 0 LOOP
      s(k)<=ql(k);
    END LOOP;
  FOR k IN WIDTH2-1 DOWNTO 0 LOOP
      s(k+WIDTH1)<=u2(k);
    END LOOP
   END PROCESS;
    sum<=s;
END flex;


Error:Line82:File d:\c++\vhdl\add_lp\add_lp.vhd:VHDl syntax error:unexpected end-of-file-try using the Text Editor's syntax Coloring command to find the missing delimiter or keyword
點(diǎn)擊錯誤時(shí),光標(biāo)就回到--LIBRARY lpm;處
怎么也不明白library lpm有什么錯,請高手指點(diǎn)一下

我用的是:MAX+plus II工具
     
2樓： >>參與討論
xing198200
誰能告訴我錯在那兒如何改正
 

LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY add_lp IS
GENERIC(WIDTH:INTEGER:=15;
         WIDTH1:INTEGER:=7;
         WIDTH2:INTEGER:=8;
         ONE   :INTEGER:=1);
PORT(x,y:IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
      sum:OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
      clk:IN STD_LOGIC);
END add_lp;
ARCHITECTURE flex OF add_lp IS
SIGNAL l1,l2,r1,q1
                   :STD_LOGIC_VECTOR(WIDTH1-1 DOWNTO 0);
SIGNAL l3,l4,r2,q2,u2,h2
                   :STD_LOGIC_VECTOR(WIDTH2-1 DOWNTO 0);
SIGNAL s          :STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
SIGNAL crl,cql    :STD_LOGIC_VECTOR(ONE-1 DOWNTO 0);


BEGIN
   PROCESS
    BEGIN
      WAIT UNTIL clk='1';
      FOR k IN WIDTH1-1 DOWNTO 0 LOOP
        l1(k)<=x(k);
        l2(k)<=y(k);
      END LOOP;
      FOR k IN WIDTH2-1 DOWNTO 0 LOOP
         l3(k)<=x(k+WIDTH1);
          l4(k)<=y(k+WIDTH1);
      END LOOP;
   END PROCESS;
add_1:lpm_add_sub
       GENERIC MAP(LPM_WIDTH=>WIDTH1,
                   LPM_REPRESENTATION=>"UNSIGNED",
                    LPM_DIRECTION=>"ADD")
          PORT MAP(dataa=>l1,datab=>l2,
                    result=>r1,cout=>crl(0));
reg_1:lpm_ff
       GENERIC MAP(LPM_WIDTH=>WIDTH1)
        PORT MAP(data=>r1,q=>q1,clock=>clk);
reg_2:lpm_ff
        GENERIC MAP(LPM_WIDTH=>ONE)
        PORT MAP(data=>crl,q=>cql,clock=>clk);
add_2:lpm_add_sub
        GENERIC MAP(LPM_WIDTH=>WIDTH2,
                    LPM_REPRESENTATION=>"UnSIGNED",
                    LPM_DIRECTION=>"ADD")
         PORT MAP(dataa=>l3,datab=>l4,result=>r2);
reg_3:lpm_ff
         GENERIC MAP(LPM_WIDTH=>WIDTH2)
         PORT MAP(data=>r2,q=>q2,clock=>clk);

h2<=(OTHERS=>'0';
add_3:lpm_add_sub
      GENERIC MAP(LPM_WIDTH=>WIDTH2,
                    LPM_REPRESENTATION=>"UNSIGNED",
                    LPM_DIRECTION=>"ADD")
        PORT MAP(cin=>cql(0),data=>q2,
                  datab=>h2,result=>u2);
PROCESS
  BEGIN
   WAIT UNTIL clk='1';
  FOR k IN WIDTH1-1 DOWNTO 0 LOOP
      s(k)<=ql(k);
    END LOOP;
  FOR k IN WIDTH2-1 DOWNTO 0 LOOP
      s(k+WIDTH1)<=u2(k);
    END LOOP
   END PROCESS;
    sum<=s;
END flex;


Error:Line82:File d:\c++\vhdl\add_lp\add_lp.vhd:VHDl syntax error:unexpected end-of-file-try using the Text Editor's syntax Coloring command to find the missing delimiter or keyword
點(diǎn)擊錯誤時(shí),光標(biāo)就回到--LIBRARY lpm;處
怎么也不明白library lpm有什么錯,請高手指點(diǎn)一下

我用的是:MAX+plus II工具
     
參與討論
昵稱：
討論內(nèi)容：
 
 
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