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ISPXPLD5256MX Datasheet

  • ISPXPLD5256MX

  • 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programm...

  • 92頁

  • LATTICE   LATTICE

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ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD鈩?Family
March 2006
Data Sheet
TM
Features
鈻?/div>
Flexible Multi-Function Block (MFB)
Architecture
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
SuperWIDE鈩?logic (up to 136 inputs)
Arithmetic capability
Single- or Dual-port SRAM
FIFO
Ternary CAM
鈻?/div>
Expanded In-System Programmability (ispXP鈩?
鈥?Instant-on capability
鈥?Single chip convenience
鈥?In-System Programmable via IEEE 1532
Interface
鈥?In鏗乶itely recon鏗乬urable via IEEE 1532 or
sysCONFIG鈩?microprocessor interface
鈥?Design security
鈻?/div>
sysCLOCK鈩?PLL Timing Control
鈥?Multiply and divide between 1 and 32
鈥?Clock shifting capability
鈥?External feedback capability
鈻?/div>
High Speed Operation
鈥?4.0ns pin-to-pin delays, 300MHz f
MAX
鈥?Deterministic timing
鈻?/div>
Low Power Consumption
鈥?Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
鈥?1.8V core for low dynamic power
鈻?/div>
sysIO鈩?Interfaces
鈥?LVCMOS 1.8, 2.5, 3.3V
鈥?Programmable impedance
鈥?Hot-socketing
鈥?Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
鈥?Open drain operation
鈥?SSTL 2, 3 (I & II)
鈥?HSTL (I, III, IV)
鈥?PCI 3.3
鈥?GTL+
鈥?LVDS
鈥?LVPECL
鈥?LVTTL
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX
Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
t
PD
(Propagation Delay)
t
S
(Register Set-up Time)
t
CO
(Register Clock to Out Time)
f
MAX
(Maximum Operating Frequency)
System Gates
I/Os
Packages
256 fpBGA
256
8
128K
48K
2
4.0ns
2.2ns
2.8ns
300MHz
75K
141
鈻?/div>
Easy System Integration
鈥?3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
鈥?5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
鈥?IEEE 1149.1 interface for boundary scan testing
鈥?sysIO quick con鏗乬uration
鈥?Density migration
鈥?Multiple density and package options
鈥?PQFP and 鏗乶e pitch BGA packaging
鈥?Lead-free package options
ispXPLD 5512MX
512
16
256K
96K
2
4.5ns
2.8ns
3.0ns
275MHz
150K
149/193/253
208 PQFP
256 fpBGA
484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX
768
24
384K
144K
2
5.0ns
2.8ns
3.2ns
250MHz
225K
193/317
256 fpBGA
484 fpBGA
1,024
32
512K
192K
2
5.2ns
3.0ns
3.7ns
250MHz
300K
317/381
484 fpBGA
672 fpBGA
漏 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The speci鏗乧ations and information herein are subject to change without notice.
www.latticesemi.com
1
5kmx_12.2

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