鈥?/div>
A0
Output Routing Pool
廬
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
D7
D5
Output Routing Pool
D Q
A1
A2
A3
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
D6
Logic
D Q
Global Routing Pool (GRP)
Array
D Q
GLB
D4
D3
D2
D1
D0
D Q
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
f
max
= 150 MHz Maximum Operating Frequency
t
pd
= 6.0 ns Propagation Delay
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
Description
The ispLSI 2192VL is a High Density Programmable
Logic Device containing 192 Registers, nine Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2192VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2192VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2192VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 2192VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
鈥?IN-SYSTEM PROGRAMMABLE
鈥?2.5V In-System Programmability (ISP鈩? Using
Boundary Scan Test Access Port (TAP)
鈥?Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
鈥?THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2192vl_02
1
CLK0
CLK1
CLK2
0139/2192VL
next
制造商 Lattice
產(chǎn)品種類 CPLD - 復雜可編程邏輯器件
存儲類型 EEPROM
大電池數(shù)量 192
最大工作頻率 150 MHz
延遲時間 6 ns
可編程輸入/輸出端數(shù)量 96
工作電源電壓 2.3 V to 2.7 V
電源電流 175 mA
最大工作溫度 + 70 C
最小工作溫度 0 C
封裝 / 箱體 TQFP-128
安裝風格 SMD/SMT
Supply Voltage - Max 2.7 V
Supply Voltage - Min 2.3 V
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