鈥?/div>
t
pd
= 5.0 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?5V Programmable Logic Core
鈥?ispJTAG鈩?In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
鈥?User-Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems
鈥?PCI Compatible Outputs
鈥?Open-Drain Output Option
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?Unused Product Term Shutdown Saves Power
鈥?ispLSI OFFERS THE FOLLOWING ADDED FEATURES
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Enhanced Pin Locking Capability
鈥?Three Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to
Minimize Switching Noise
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
廬
Functional Block Diagram
Output Routing Pool (ORP)
D7
D6
D5
D4
Output Routing Pool (ORP)
D3
D2
D1
D0
C7
Output Routing Pool (ORP)
A0
A1
C6
A2
D
Q
C5
A3
D
Q
C4
Output Routing Pool (ORP)
A4
D
Q
GLB
C3
A5
D
Q
C2
A6
C1
A7
B0
B1
Global Routing Pool (GRP)
B2
B3
B4
B5
B6
B7
C0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
0139(9A)/2128
Description
The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer-
sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2128E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2128E offers non-volatile reprogrammability of all logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2128E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
The device also has 128 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
Copyright 漏 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
November 1998
2128e_02
1
Output Routing Pool (ORP)
Logic
Array
Output Routing Pool (ORP)
LATTICE
1
2
3
4
5
6
7
8
9
10
11
