鈥?/div>
t
pd
= 5.5 ns Propagation Delay
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?Unused Product Term Shutdown Saves Power
鈥?IN-SYSTEM PROGRAMMABLE
鈥?2.5V In-System Programmability (ISP鈩? Using
Boundary Scan Test Access Port (TAP)
鈥?Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
鈥?THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
鈥?Enhanced Pin Locking Capability
鈥?Three Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
廬
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C7
A0
C6
C5
C4
C3
C2
C1
C0
B7
Output Routing Pool (ORP)
D Q
A1
A2
GLB
Logic
Array
D Q
B6
D Q
Global Routing Pool
(GRP)
B5
D Q
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096VL
Description
The ispLSI 2096VL is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2096VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2096VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control, and
the output drivers can source 4 mA or sink 8 mA. Each
output can be programmed independently for fast or slow
output slew rate to minimize overall output switching
Copyright 漏 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2096vl_02
1
Output Routing Pool (ORP)
LATTICE
1
2
3
4
5
6
7
8
9
10
11
