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ISPLSI1024-60LH/883 Datasheet

  • ISPLSI1024-60LH/883

  • In-System Programmable High Density PLD

  • 148.99KB

  • 12頁(yè)

  • LATTICE   LATTICE

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ispLSI 1024/883
廬
In-System Programmable High Density PLD
Features
鈥?HIGH-DENSITY PROGRAMMABLE LOGIC
鈥?High-Speed Global Interconnect
鈥?4000 PLD Gates
鈥?48 I/O Pins, Six Dedicated Inputs
鈥?144 Registers
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Fast Random Logic
鈥?Security Cell Prevents Unauthorized Copying
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 60 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 20 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile E
2
CMOS Technology
鈥?100% Tested
鈥?IN-SYSTEM PROGRAMMABLE
鈥?In-System Programmable鈩?(ISP鈩? 5-Volt Only
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Debugging
鈥?COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Four Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
unctional
Block
Functional Block Diagram
A0
C7
C6
C5
GLB
Output Routing Pool
A1
A2
A3
A4
A5
A6
A7
Logic
Array
D Q
D Q
C4
C3
C2
C1
D Q
Global Routing Pool (GRP)
C0
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
CLK
0139-A-isp
Description
The ispLSI 1024/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 144 Registers,
48 Universal I/O pins, six Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1024/883
features 5-Volt in-system programmability and in-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 1024/883 device is
the Generic Logic Block (GLB). The GLBs are labeled A0,
A1 .. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Diagram
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
1024MIL_01
1
Output Routing Pool
D Q

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