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ISPGDX160-7Q208 Datasheet

  • ISPGDX160-7Q208

  • In-System Programmable Generic Digital CrosspointTM

  • 25頁

  • LATTICE   LATTICE

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ispGDX Family
TM
In-System Programmable
Generic Digital Crosspoint
Features
鈥?IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
鈥?Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
鈥?Three Device Options: 80 to 160 Programmable I/O
Pins
鈥?鈥淎ny Input to Any Output鈥?Routing
鈥?Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
鈥?Space-Saving TQFP, PQFP and BGA Packaging
鈥?Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
鈥?PCI Compliant Output Drive
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?5V Power Supply
鈥?5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
鈥?Low-Power: 40mA Quiescent Icc
鈥?Balanced 24mA Output Buffers with Programmable
Slew Rate Control
鈥?Schmitt Trigger Inputs for Noise Immunity
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile E
2
CMOS Technology
鈥?100% Tested
鈥?ispGDX OFFERS THE FOLLOWING ADVANTAGES
鈥?In-System Programmable
鈥?Lattice ISP or JTAG Programming Interface
鈥?Only 5V Power Supply Required
鈥?Change Interconnects in Seconds
鈥?Reprogram Soldered Devices
鈥?FLEXIBLE ARCHITECTURE
鈥?Combinatorial/Latched/Registered Inputs or Outputs
鈥?Individual I/O Tri-state Control with Polarity Control
鈥?Dedicated Clock Input Pins (two or four) or
Programmable Clocks from I/O Pins (from 20 up to
40)
鈥?Up to 4:1 Dynamic Path Selection
鈥?Programmable Output Pull-up Resistors
鈥?Outputs Tri-state During Power-up (鈥淟ive Insertion鈥?/div>
Friendly)
鈥?DESIGN SUPPORT THROUGH LATTICE鈥橲 ispGDX
DEVELOPMENT SOFTWARE
鈥?MS Windows or NT / PC-Based or Sun O/S
鈥?Easy Text-Based Design Entry
鈥?Automatic Signal Routing
鈥?Program up to 100 ISP Devices Concurrently
鈥?Simulator Netlist Generation for Easy Board-Level
Simulation
TM
Functional Block Diagram
I/O Pins D
ISP
Control
I/O Pins C
I/O Pins A
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
Boundary
Scan
Control
I/O Pins B
Description
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
鈥?Multi-Port Multiprocessor Interfaces
鈥?Wide Data and Address Bus Multiplexing
(e.g. 4:1 High-Speed Bus MUX)
鈥?Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc)
鈥?Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Copyright 漏 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
ispgdx_08
1

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