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ASM3I623S00AG-08-TR Datasheet

  • ASM3I623S00AG-08-TR

  • Zero Cycle Slip Peak EMI reduction IC

  • 16頁

  • ALSC

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July 2005
rev 1.0
ASM3P623S00A/B/C/D/E/F
Operating Conditions for ASM3P623S00A/B/C and ASM3P623S00D/E/F Devices
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
0
Max
3.6
70
30
7
Unit
V
擄C
pF
pF
Electrical Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
Description
Input LOW Voltage
5
Input HIGH Voltage
5
Input LOW Current
Input HIGH Current
Output LOW Voltage
6
Output HIGH Voltage
6
Supply Current
Output Impedance
V
IN
= 0V
Test Conditions
Min
2.0
Typ
Max
0.8
50
100
0.4
Unit
V
V
碌A(chǔ)
碌A(chǔ)
V
V
mA
鈩?/div>
V
IN
= VDD
I
OL
= 8mA
I
OH
= -8mA
Unloaded outputs
2.4
15
23
Switching Characteristics for ASM3P623S00A/B/C and ASM3P623S00D/E/F
7
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Notes:
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. All parameters specified with loaded outputs.
Description
Output Frequency
Duty Cycle
6
= (t
2
/ t
1
) * 100
Output Rise Time
6
Output Fall Time
6
Output-to-output skew
6
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
6
Test Conditions
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at VDD /2
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
20
40
Typ
50
Max
50
60
2.5
2.5
250
鹵350
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Device-to-Device Skew
6
Cycle-to-cycle jitter
6
PLL Lock Time
6
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
5 of 16

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