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ASM3I623S00AG-08-TR Datasheet

  • ASM3I623S00AG-08-TR

  • Zero Cycle Slip Peak EMI reduction IC

  • 16頁

  • ALSC

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July 2005
rev 1.0
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
ASM3P623S00A/B/C/D/E/F
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P623S00X
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below
the
reference
frequency
with
a
specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation
Cycle Slip
Cycle slip occurs when the output clock edge
鈥榳anders鈥?away from the corresponding input clock
edge. There are two types of cycle slips 鈥?a Differential
cycle slip and an Integral cycle slip. The differential
cycle slip is caused due the clock edge variation over
one modulation cycle. It is defined by the maximum
amount of 鈥榳ander鈥?the clock edge will have within one
modulation cycle. Integral cycle slip occurs due to the
accumulation of the cycle slip over successive modulation
cycles. In ASM3P623S00A/B/C/D/E/F the differential cycle
slip is within the value mentioned in the
鈥?/div>
Differential Cycle
Slip and Spread Spectrum Control Table鈥?and the Integral
Cycle Slip is 鈥榋ero鈥?
Pin Configuration
CLKIN
NC
SS%
GND
1
2
3
4
8
NC
V
DD
CLKOUT
SSON
ASM3P623S00A/B/C
7
6
5
CLKIN
CLKOUT1
VDD
SS%
GND
CLKOUT2
CLKOUT3
DLY CNTRL
1
2
3
4
5
6
7
8
16
15
14
CLKOUT8
CLKOUT7
CLKOUT6
VDD
GND
CLKOUT5
CLKOUT4
SSON
ASM3P623S00 D/E/F
13
12
11
10
9
Zero Cycle Slip Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 16

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