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PD064VT5

7-4) Input / Output signal timing chart

Parameters

CLK

Frequency

Period

Display period

Pulse width

Back-porch

Front-porch

Hpw+Hbp

Hsync-CLK

Vsync-Hsync

Symbol

Fc=1/Tc

tc

Hp

Hd

Hpw

Hbp

Hfp

Hhc

Hvh

Format

All

All

All

All

All

All

All

All

All

All

480

Period

Vp

400

350

Display period

Vsync

Pulse width

Back-porch

Vdp

Vpw

Vbp

480

400

350

All

480

400

350

480

400

350

480

400

350

All

All

All

All

All

All

Min.

-

-

-

-

-

12

12

-

136

10

0

-

515

-

446

-

447

-

-

-

2

2

2

2

1

1

1

31

33

58

10

10

780

-

-

515

Typ.

25.175

40

31.778

800

640

96

48

16

144

-

0

16.8

525

14.3

449

14.3

449

480

400

350

2

33

35

60

10

12

37

35

37

62

Max.

-

-

-

-

-

139

139

-

151

Tc-10

200

-

800

-

480

-

510

-

-

-

35

35

38

63

-

-

-

38

40

65

-

-

900

-

-

800

Unit

MHz

ns

us

tc

tc

tc

tc

tc

tc

ns

tc

ms

Hp

ms

Hp

ms

Hp

Hp

Hp

Hp

Note

Note 7-7

Hsync

Front-porch

Vfp

Hp

Vpw+Vbp

Data

CLK-DATA

DATA-CLK

Horizontal scanning

period

Horizontal display

period

Vertical display

period

Frame cycling

period

Dcd

Ddc

T1

T2

T3

T4

Hp

ns

ns

tc

tc

T1

T1

800

640

480

525

DENB

Note 7-7 : Tc is the period of sampling clock. In case of low-frequency , the image-flicker may occur.

The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed,

reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd. Page:8

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