TDA7461N
NOISE BLANKER PART
internal 2nd order 140kHz high pass filter
programmable trigger threshold
additional circuits for trigger adjustment (devia-
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
V
TR
Parameter
Trigger Threshold
0) 1)
Test Condition
meas. with V
PEAK
= 0.9V
Min.
NBT = 111
NBT = 110
NBT = 101
NBT = 100
NBT = 011
NBT = 010
NBT = 001
NBT = 000
NCT = 00
NCT = 01
NCT = 10
NCT = 11
0.5
1.5
2.2
0.5
0.9
1.7
2.5
0.5
1.0
1.5
2.0
Typ.
30
35
40
45
50
55
60
65
260
220
180
140
0.9
1.7
2.5
0.9(off)
1.2
2.0
2.8
0.9(off)
1.3
1.8
2.3
Max.
Unit
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
mV
OP
V
V
V
V
OP
V
OP
V
OP
V
OP
V
V
V
V
tion, field-strenght)
very low offset current during hold time
four selectable pulse suppression times
V
TRNOISE
Noise Controlled Trigger
Threshold
2)
meas. with V
PEAK
= 1.5V
V
RECT
Rectifier Voltage
V
RECT DEV
deviation dependent
3)
rectifier Voltage
V
RECT FS
Fieldstrength Controlled
Rectifier Voltage
4)
V
MPX
= 0mV
V
MPX
= 50mV; f = 150KHz
V
MPX
= 100mV; f = 150KHz
OVD = 11
means. with
V
MPX
= 800mV
OVD = 10
(75KHz dev.)
OVD = 01
OVD = 00
FSC = 11
means. with
V
MPX
= 0mV
FSC = 10
V
LEVEL
<< V
SBL
FSC = 01
(fully mono)
FSC = 00
1.3
2.1
2.9
1.3
1.5
2.3
3.1
1.3
1.6
2.1
2.6
0) All thresholds are measured using a pulse with T
R
= 2
碌
s, T
HIGH
= 2
碌
s and T
F
= 10
碌
s.
1) NBT represents the Noiseblanker-Byte bits D2; D0 for the noise blanker trigger threshold
2) NAT represents the Noiseblanker-Byte bit pair D4,D3 for the noise controlled trigger adjustment
3) OVD represents the Noiseblanker-Byte bit pair D7,D6 for the over deviation detector
4) FSC represents the Fieldstrength-Byte bit pair D1,D0 for the fieldstrength control
V IN
VOP
DC
D97AU636
TR
THIGH
TF
Time
14/31