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TDA7313ND Datasheet

  • TDA7313ND

  • DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS

  • 14頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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TDA7313N
Figure 18:
Timing Diagram of I
2
CBUS
Figure 19:
Acknowledge on the I
2
CBUS
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte, containing the TDA7313N
address (the 8th bit of the byte must be 0). The
TDA7313N must always acknowledge at the
end of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
TDA7313N ADDRESS
MSB
S
1
0
first byte
0
0
1
0
0
LSB
0
ACK
MSB
DATA
LSB
ACK
MSB
DATA
LSB
ACK
P
Data Transferred (N-bytes + Acknowledge)
ACK = Acknowledge
S = Start
P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION
Chip address
1
MSB
0
0
0
1
0
0
0
LSB
DATA BYTES
MSB
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
B2
0
1
0
1
0
1
1
B1
B1
B1
B1
B1
G1
0
1
B0
B0
B0
B0
B0
G0
C3
C3
A2
A2
A2
A2
A2
S2
C2
C2
A1
A1
A1
A1
A1
S1
C1
C1
LSB
A0
A0
A0
A0
A0
S0
C0
C0
FUNCTION
Volume control
Speaker ATT LR
Speaker ATT RR
Speaker ATT LF
Speaker ATT RF
Audio switch
Bass control
Treble control
Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 3.75dB steps
9/14

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