蠅 鈥?/div>
C
RMS
(3b)
Table 1 illustrates that the boost capacitor ripple current
can be reduced by about 50% at nominal line and about
30% at high line with the synchronization scheme facili-
tated by the UCC3858. The output capacitance value can
be significantly reduced if its choice is dictated by ripple
current or the capacitor life can be increased as a result.
In cost sensitive designs where hold-up time is not criti-
cal, this is a significant advantage.
An alternative method of synchronization to achieve the
same ripple reduction is possible. In this method, the
turn-on of Q1 is synchronized to the turn-off of Q2. While
this method yields almost identical ripple reduction and
maintains trailing edge modulation on both converters,
the synchronization is much more difficult to achieve and
the circuit can become susceptible to noise as the syn-
chronizing edge itself is being modulated.
Reference Signal (I
MULT
) Generation
Like the UC3854 series, the UCC3858 has an Analog
Computation Unit (ACU) which generates a reference
current signal for the current error amplifier. The inputs to
the ACU are (signals proportional to) instantaneous line
voltage, input voltage RMS information and the voltage
error amplifier output. Unlike prior techniques of RMS
voltage sensing, UCC3858 employs a patent pending
technique to simplify the RMS voltage generation and
eliminate performance degradation caused by the prior
techniques. With the novel technique (shown in Fig. 7),
need for external two pole filter for V
RMS
generation is
eliminated. Instead, the IAC current is mirrored and used
to charge an external capacitor (C
RMS
) during a half cy-
cle. The voltage on CRMS takes the integrated sinusoidal
shape and is given by equation 3. At the end of the half-
cycle, CRMS voltage is held and converted into a 4-bit
digital word for further processing in the ACU. CRMS is
discharged and readied for integration during the next
half cycle. The advantage of this method is that the sec-
ond harmonic ripple on the V
RMS
signal is virtually elimi-
nated. Such second harmonic ripple is unavoidable with
the limited roll-off of a conventional 2-pole filter and re-
sults in a 3rd harmonic distortion in the input current sig-
nal. The dynamic response to the input line variations is
also improved as a new V
RMS
signal is generated every
cycle.
LINE
V
CRMS
ADC
HOLD
R
AC
IAC
1
A
V
AO
B
C
CRMS
2
A鈥
C
C
RMS
A
D
4 BIT
WORD
REGISTER
MULTI
DAC
(X
2
)
Figure 7. Novel circuit for RMS signal generation.
For proper operation, I
ACpk
should be selected to be
100碌A(chǔ) at peak line voltage. For universal input voltage
with peak value of 265 VAC, this means R
AC
= 3.6M. The
noise sensitivity of the IC requires a small bypass capaci-
tor for high frequency noise filtering. The value of this ca-
pacitor should be limited to 330pF maximum. The V
CRMS
value should be approximately 1V at the peak of low line
(80 VAC) to minimize any digitization errors. The peak
value of V
CRMS
at high line then becomes 3.5V. The de-
sired C
RMS
can be calculated from equation 3 to be 90nF
for 50Hz line and 75nF for 60Hz line.
The multiplier output current is given by equation (4) with
K=0.33.
I
MULT
=
(
V
VAO
鈥?1)
鈥?/div>
I
AC
鈥?/div>
K
(4)
V
CRMS
2
The multiplier peak current is limited to 200碌A(chǔ) and the
selected values for I
AC
and V
CRMS
should ensure that
the current is within this range. Another limitation of the
multiplier is that I
MULT
can not exceed two times the I
AC
current, limiting the minimum voltage on V
CRMS
.
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