UCC1858
UCC2858
UCC3858
PIN DESCRIPTIONS (cont.)
VDD:
(Positive Supply Voltage) Connect to a stable
source of at least 20mA between 13V and 17V for normal
operation. Bypass VDD directly to GND to absorb supply
current spikes required to charge external MOSFET gate
capacitance. To prevent inadequate gate drive signals,
the output devices will be inhibited unless V
VDD
exceeds
the upper undervoltage lockout voltage threshold and re-
mains above the lower threshold.
VREF:
(Reference Voltage) VREF is the output of an ac-
curate 7.5V voltage reference. This output is capable of
delivering 10mA to peripheral circuitry and is internally
short circuit current limited. VREF is disabled and will re-
main at 0V when V
VDD
is low. Bypass VREF to GND with
a 0.1碌F or larger ceramic capacitor for best stability.
APPLICATION INFORMATION
The UCC3858 is designed to optimize the implementa-
tion of power factor corrected boost converters in low to
medium power applications where light load efficiency is
critical. While basic configuration of the UCC3858 is simi-
lar to the industry standard UC3854 series controllers,
several distinguishing features have been added. A typi-
cal application circuit is shown along with a diagram
showing how the UCC3858 can be used with the down-
stream converter to achieve optimum performance.
Chip Bias Supply and Startup
The UCC3858 is implemented using Unitrode鈥檚
BCDMOS process allowing minimal startup (60碌A typi-
cal) and operating (3.5mA typical) supply currents. This
results in significantly lower power consumption in the
trickle charge resistor used to startup the IC, increasing
the system efficiency at light loads. Lower supply cur-
rents, coupled with the wide undervoltage lockout hyster-
esis (13.75V on, 10V off) provide the opportunity to
operate both stages from the same startup and bootstrap
supply as shown in the typical application drawing.
Oscillator and Frequency Foldback at Light Loads
The oscillator of the UCC3858 is set up to operate either
synchronously with the downstream converter or as a
stand alone oscillator. A simplified block diagram of the
oscillator and associated circuitry is shown in Fig. 2 and
the related waveforms are shown in Fig. 3a - 3c. A rising
edge at the SYNC pin initiates the clock cycle by charg-
ing up the CT pin with a nominal internal current of
I
CHnom
(=19 鈥
DIS
). Once the high threshold of the ramp
(4.5V) is crossed, the internal latch is set and the CT pin
starts discharging at a rate (I
DIS
=3/R
T
) set by the resistor
on the RT pin. In the absence of a SYNC pulse, C
T
dis-
charges all the way to the ramp low threshold (1V) and
that sets the free running frequency of the oscillator as
given by equation 1. In applications where synchroniza-
tion is used, the R
T
, C
T
values should be chosen so that
the free running frequency is always lower than the syn-
chronization frequency.
When VAO falls below the threshold level set by FBL, the
oscillator goes into frequency foldback mode and dis-
ables synchronization. The frequency foldback is
achieved by reducing the oscillator charging current as
the power level (and VAO voltage) falls. As shown in Fig.
2, the difference between VAO and FBL regulates cur-
rent I
Csub
which subtracts the current available for charg-
ing C
T
. The effective charge current into the capacitor is
given by (I
CHnom
- I
Csub
). To avoid converter operation in
the low frequency range (e.g. audio), the charge current
should not be allowed to go very low. Minimum frequency
of the controller is programmed by the current I
MIN
flow-
ing into pin FBM which sets the minimum charging cur-
rent. The value of R
FBM
to set the desired minimum
frequency is given by:
R
FBM
=
3
1
鈥?/div>
鈥?/div>
R
T
3.5
f
MIN
鈥?/div>
C
T
(2)
Fig. 4 shows the characteristic curves for the frequency
foldback. When the converter comes out of the low
power mode, the time taken to restore normal mode op-
eration (return to nominal or synchronized frequency op-
eration) must be minimized. Given that the voltage error
amplifier response is very slow in PFC circuits, the VAO
pin change is not the best indicator of change in load
conditions. UCC3858 provides a solution where the nor-
mal mode can be restored instantaneously when FBM is
pulled below 1.5V. A typical interface would involve the
output of the error amplifier of the downstream converter
(with proper buffering and filtering) driving an npn switch
that pulls FBM down to GND. The buffer and filter should
ensure that the switch is turned on only when the error
amplifier of downstream converter is saturated high for a
preset duration indicating a droop in output voltage from
increased load. The FBM input can also be permanently
pulled low to disable the frequency foldback mode com-
pletely, while still using the other features of UCC3858.
FBL pin also acts as a chip disable input when it is
brought below 0.5V.
f
=
19
3
1
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