MCP601/602/603/604
Note:
Unless otherwise indicated, V
DD
= +2.7V to +5.5V, T
A
= 25擄C, V
CM
= V
DD
/2, R
L
= 25k鈩?to V
DD
/2 and V
OUT
~ V
DD
/2
240
220
200
Offset Voltage (碌V)
180
160
140
120
100
80
60
40
-1
0
1
2
3
4
5
Common Mode Voltage (V)
V
DD
= 2.7V
V
DD
= 5.5V
Representative Part
100
PSRR+
80
PSRR, CMRR (dB)
PSRR-
CMRR
V
DD
=5.0V,
C
L
=50 pF
60
40
20
0
-20
1
1
10
10
100
100
1K
1000
10K
10000
100K
100000
1M
10M
1000000 10000000
Frequency (Hz)
FIGURE 2-13:
Offset Voltage vs. Common-Mode
Voltage
FIGURE 2-16:
Common-Mode
Rejection
Power Supply Rejection Ratio vs. Frequency
Ratio,
20
Input Bias Current, Input Offset Current (pA)
18
16
14
12
10
8
6
4
2
0
-40
-20
0
20
40
60
80
Input Bias Current Levels are Typically
less than 1pA Below 25擄C
Input Bias Current
V
DD
= 5.5V
Input Bias, Input Offset Current (pA)
20
18
16
14
12
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Common-mode Voltage (V)
Input Offset
V
DD
= 5.5V
R
L
=
鈭?/div>
T
A
= 85 擄C
Input Bias Current
Input
Offset
Current
Temperature (擄C)
FIGURE 2-14:
Input Bias Current, Input Offset
Current vs. Temperature
FIGURE 2-17:
Input Bias Current, Input Offset
Current vs. Common Mode Input Voltage
120
V
DD
= 5.5V
DC Open Loop Gain (dB)
115
110
Open Loop Gain (dB)
110
V
DD
= 2.7V
100
105
100
90
95
80
90
0
0
2K
20000
4K
40000
6K
60000
8K
80000
10K
100000
2
2.5
3
3.5
4
4.5
5
5.5
Load Resistance (鈩?
Power Supply Voltage, V
DD
(V)
FIGURE 2-15:
DC Open Loop Gain vs. Output Load
FIGURE 2-18:
DC Open Loop Gain vs. Power Supply
DS21314D-page 6
錚?/div>
2000 Microchip Technology Inc.
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