音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5鈥?1
External Timing I/O Delay Adders
The I/O delay timing parameters for I/O standard input and output adders, and
input delays are specified by speed grade independent of device density.
Table 5鈥?7
through
Table 5鈥?8
show the adder delays associated with I/O pins for all
packages. The delay numbers for 鈥?, 鈥?, and 鈥? speed grades shown in
Table 5鈥?7
through
Table 5鈥?0
are based on an EPM1270 device target, while 鈥? and 鈥? speed
grade values are based on an EPM570Z device target. If an I/O standard other than
3.3-V LVTTL is selected, add the input delay adder to the external t
SU
timing
parameters shown in
Table 5鈥?3
through
Table 5鈥?6.
If an I/O standard other than
3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output
delay adder to the external t
CO
and t
PD
shown in
Table 5鈥?3
through
Table 5鈥?6.
Table 5鈥?7.
External Timing Input Delay Adders
鈥? Speed
Grade
Standard
3.3-V LVTTL
Without Schmitt
Trigger
With
Schmitt Trigger
3.3-V
LVCMOS
Without Schmitt
Trigger
With
Schmitt Trigger
2.5-V LVTTL
Without Schmitt
Trigger
With Schmitt
Trigger
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
Without Schmitt
Trigger
Without Schmitt
Trigger
Without Schmitt
Trigger
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
23
339
291
681
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
30
441
378
885
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
37
543
466
1,090
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
42
429
378
681
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
43
476
373
622
0
ps
ps
ps
ps
ps
鈥?/div>
鈥?/div>
0
334
鈥?/div>
鈥?/div>
0
434
鈥?/div>
鈥?/div>
0
535
鈥?/div>
鈥?/div>
0
387
鈥?/div>
鈥?/div>
0
434
ps
ps
Min
鈥?/div>
鈥?/div>
Max
0
334
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
0
434
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
0
535
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
0
387
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
0
434
Unit
ps
ps
Table 5鈥?8.
MAX II IOE Programmable Delays
鈥? Speed
Grade
Parameter
Input Delay from Pin to Internal
Cells = 1
Input Delay from Pin to Internal
Cells = 0
Min
鈥?/div>
鈥?/div>
Max
1,225
89
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
1,592
115
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
1,960
142
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
1,858
569
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
Max
2,171
609
Unit
ps
ps
漏 Novermber 2008 Altera Corporation
MAX II Device Handbook

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

EPM240T100C5N相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！