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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 1035.40KB

  • 101頁(yè)

  • Altera   Altera

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5鈥?4
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5鈥?1.
UFM Block Internal Timing Microparameters (Part 1 of 2)
鈥? Speed
Grade
Symbol
t
ACLK
t
ASU
t
AH
t
ADS
t
ADH
t
DCLK
t
DSS
t
DSH
t
DDS
t
DDH
t
DP
t
PB
Parameter
Address register clock period
Address register shift signal setup
to address register clock
Address register shift signal hold to
address register clock
Address register data in setup to
address register clock
Address register data in hold from
address register clock
Data register clock period
Data register shift signal setup to
data register clock
Data register shift signal hold from
data register clock
Data register data in setup to data
register clock
Data register data in hold from data
register clock
Program signal to data clock hold
time
Maximum delay between program
rising edge to UFM busy signal
rising edge
Minimum delay allowed from UFM
busy signal going low to program
signal going low
Maximum length of busy pulse
during a program
Minimum erase signal to address
clock hold time
Maximum delay between the erase
rising edge to the UFM busy signal
rising edge
Minimum delay allowed from the
UFM busy signal going low to erase
signal going low
Maximum length of busy pulse
during an erase
Delay from data register clock to
data register output
Min
100
20
20
20
20
100
60
20
20
20
0
鈥?/div>
Max
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
960
鈥? Speed
Grade
Min
100
20
20
20
20
100
60
20
20
20
0
鈥?/div>
Max
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
960
鈥? Speed
Grade
Min
100
20
20
20
20
100
60
20
20
20
0
鈥?/div>
Max
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
960
鈥? Speed
Grade
鈥? Speed
Grade
Max Unit
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
960
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Max Min
100
20
20
20
20
100
60
20
20
20
0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
960
100
20
20
20
20
100
60
20
20
20
0
鈥?/div>
t
BP
20
鈥?/div>
20
鈥?/div>
20
鈥?/div>
20
鈥?/div>
20
鈥?/div>
ns
t
PPMX
t
AE
t
EB
鈥?/div>
0
鈥?/div>
100
鈥?/div>
960
鈥?/div>
0
鈥?/div>
100
鈥?/div>
960
鈥?/div>
0
鈥?/div>
100
鈥?/div>
960
鈥?/div>
0
鈥?/div>
100
鈥?/div>
960
鈥?/div>
0
鈥?/div>
100
鈥?/div>
960
碌s
ns
ns
t
BE
20
鈥?/div>
20
鈥?/div>
20
鈥?/div>
20
鈥?/div>
20
鈥?/div>
ns
t
EPMX
t
DCO
鈥?/div>
鈥?/div>
500
5
鈥?/div>
鈥?/div>
500
5
鈥?/div>
鈥?/div>
500
5
鈥?/div>
鈥?/div>
500
5
鈥?/div>
鈥?/div>
500
5
ms
ns
MAX II Device Handbook
漏 Novermber 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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