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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁(yè)

  • Altera   Altera

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5鈥?0
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5鈥?3.
MAX II Device Timing Model Status
Device
EPM1270
EPM2210
Note to
Table 5鈥?3:
(1) The MAX IIZ device timing models are only available in the Quartus II software version
8.0 and later.
Preliminary
鈥?/div>
鈥?/div>
Final
v
v
Performance
Table 5鈥?4
shows the MAX II device performance for some common designs. All
performance values were obtained with the Quartus II software compilation of
megafunctions. Performance values for 鈥?, 鈥?, and 鈥? speed grades are based on an
EPM1270 device target while 鈥? and 鈥? speed grades are based on an EPM570Z device
target.
Table 5鈥?4.
MAX II Device Performance
Resources Used
Resource
Used
LE
Design Size and
Function
16-bit counter
(1)
64-bit counter
(1)
16-to-1 multiplexer
32-to-1 multiplexer
16-bit XOR function
16-bit decoder with
single address line
UFM
512 脳 16
512 脳 16
512 脳 8
512 脳 16
Notes to
Table 5鈥?4:
(1) This design is a binary loadable up counter.
(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of LEs used.
(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.
(4) This design is asynchronous.
(5) The I
2
C megafunction is verified in hardware up to 100-kHz serial clock line (SCL) rate.
Performance
鈥?
Speed
Grade
304.0
201.5
6.0
7.1
5.1
5.2
10.0
8.0
(4)
100
(5)
鈥?
Speed
Grade
247.5
154.8
8.0
9.0
6.6
6.6
10.0
8.0
(4)
100
(5)
鈥?
Speed
Grade
201.1
125.8
9.3
11.4
8.2
8.2
10.0
8.0
(4)
100
(5)
鈥?
Speed
Grade
184.1
83.2
17.4
12.5
9.0
9.2
10.0
9.7
(4)
100
(5)
鈥?
Speed
Grade
123.5
83.2
17.3
22.8
15.0
15.0
10.0
9.7
(4)
100
(5)
Mode
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
None
SPI
(2)
Parallel
(3)
I
2
C
(3)
LEs
16
64
11
24
5
5
3
37
73
142
UFM
Blocks
0
0
0
0
0
0
1
1
1
1
Unit
MHz
MHz
ns
ns
ns
ns
MHz
MHz
MHz
kHz
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device
density.
Table 5鈥?5
through
Table 5鈥?2
describe the MAX II device internal timing
microparameters for logic elements (LEs), input/output elements (IOEs), UFM
structures, and MultiTrack interconnects. The timing values for 鈥?, 鈥?, and 鈥? speed
grades shown in
Table 5鈥?5
through
Table 5鈥?2
are based on an EPM1270 device
target, while 鈥? and 鈥? speed grade values are based on an EPM570Z device target.
MAX II Device Handbook
漏 Novermber 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤(pán)

  • 544-1964EPM240T100C5N-ND

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