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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 1035.40KB

  • 101頁(yè)

  • Altera   Altera

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Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5鈥?
Figure 5鈥?.
MAX II Device Timing Model
Output and Output Enable
Data Delay
t
R4
Data-In/LUT Chain
User
Flash
Memory
Logic Element
LUT Delay
t
IODR
t
IOE
t
C4
Output Routing
Delay
t
LOCAL
t
LUT
Register Control
Delay
t
COMB
t
CO
t
SU
t
H
t
PRE
t
CLR
t
FASTIO
I/O Input Delay
t
IN
Input Routing
Delay
t
DL
Output
Delay
t
OD
t
XZ
t
ZX
I/O Pin
t
C
I/O Pin
INPUT
t
GLOB
Global Input Delay
To Adjacent LE
Register Delays
From Adjacent LE
Combinational Path Delay
Data-Out
The timing characteristics of any signal path can be derived from the timing model
and parameters of a particular device. External timing parameters, which represent
pin-to-pin timing delays, can be calculated as the sum of internal parameters.
f
Refer to the
Understanding Timing in MAX II Devices
chapter in the
MAX II Device
Handbook
for more information.
This section describes and specifies the performance, internal, external, and UFM
timing specifications. All specifications are representative of the worst-case supply
voltage and junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus
廬
II software
issues an informational message during the design compilation if the timing models
are preliminary.
Table 5鈥?3
shows the status of the MAX II device timing models.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 5鈥?3.
MAX II Device Timing Model Status
Device
EPM240
EPM240Z
(1)
EPM570
EPM570Z
(1)
Preliminary
鈥?/div>
v
鈥?/div>
v
Final
v
鈥?/div>
v
鈥?/div>
漏 Novermber 2008 Altera Corporation
MAX II Device Handbook

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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