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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

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4鈥?
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
Power-Up Characteristics
When power is applied to a MAX II device, the POR circuit monitors V
CCINT
and
begins SRAM download at an approximate voltage of 1.7 V or 1.55 V for MAX IIG and
MAX IIZ devices. From this voltage reference, SRAM download and entry into user
mode takes 200 to 450 碌s maximum, depending on device density. This period of time
is specified as t
CONFIG
in the power-up timing section of the
DC and Switching
Characteristics
chapter in the
MAX II Device Handbook.
Entry into user mode is gated by whether all V
CCIO
banks are powered with sufficient
operating voltage. If V
CCIN
T and V
CCIO
are powered simultaneously, the device enters
user mode within the t
CONFIG
specifications. If V
CCIO
is powered more than t
CONFIG
after
V
CCINT
, the device does not enter user mode until 2 碌s after all V
CCIO
banks are powered.
For MAX II and MAX IIG devices, when in user mode, the POR circuitry continues to
monitor the V
CCINT
(but not V
CCIO
) voltage level to detect a brown-out condition. If
there is a V
CCINT
voltage sag at or below 1.4 V during user mode, the POR circuit resets
the SRAM and tri-states the I/O pins. Once V
CCINT
rises back to approximately 1.7 V
(or 1.55 V for MAX IIG devices), the SRAM download restarts and the device begins
to operate after t
CONFIG
time has passed.
For MAX IIZ devices, the POR circuitry does not monitor the V
CCINT
and V
CCIO
voltage
levels after the device enters user mode. If there is a V
CCINT
voltage sag below 1.4 V
during user mode, the functionality of the device will not be guaranteed and you
must power down the V
CCINT
to 0 V for a minimum of 10 碌s before powering the V
CCINT
and V
CCIO
up again. Once V
CCINT
rises from 0 V back to approximately 1.55 V, the
SRAM download restarts and the device begins to operate after t
CONFIG
time has
passed.
Figure 4鈥?
shows the voltages for POR of MAX II, MAX IIG, and MAX IIZ devices
during power-up into user mode and from user mode to power-down or brown-out.
1
All V
CCINT
and V
CCIO
pins of all banks must be powered on MAX II devices before
entering user mode.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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