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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁(yè)

  • Altera   Altera

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4鈥?
Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Hot Socketing Feature Implementation in MAX II Devices
I/O Pins Remain Tri-Stated during Power-Up
A device that does not support hot-socketing may interrupt system operation or cause
contention by driving out before or during power-up. In a hot socketing situation, the
MAX II device鈥檚 output buffers are turned off during system power-up. MAX II
devices do not drive out until the device attains proper operating conditions and is
fully configured. Refer to
鈥淧ower-On Reset Circuitry鈥?on page 4鈥?
for information
about turn-on voltages.
Signal Pins Do Not Drive the V
CCIO
or V
CCINT
Power Supplies
MAX II devices do not have a current path from I/O pins or
GCLK[3..0]
pins to the
V
CCIO
or V
CCINT
pins before or during power-up. A MAX II device may be inserted into
(or removed from) a system board that was powered up without damaging or
interfering with system-board operation. When hot socketing, MAX II devices may
have a minimal effect on the signal integrity of the backplane.
AC and DC Specifications
You can power up or power down the V
CCIO
and V
CCINT
pins in any sequence. During
hot socketing, the I/O pin capacitance is less than 8 pF. MAX II devices meet the
following hot socketing specifications:
鈻?/div>
鈻?/div>
The hot socketing DC specification is: | I
IOPIN
| < 300
渭A.
The hot socketing AC specification is: | I
IOPIN
| < 8 mA for 10 ns or less.
1
MAX II devices are immune to latch-up when hot socketing. If the
TCK
JTAG input
pin is driven high during hot socketing, the current on that pin might exceed the
specifications above.
I
IOPIN
is the current at any user I/O pin on the device. The AC specification applies
when the device is being powered up or powered down. This specification takes into
account the pin capacitance but not board trace and external loading capacitance.
Additional capacitance for trace, connector, and loading must be taken into
consideration separately. The peak current duration due to power-up transients is
10 ns or less.
The DC specification applies when all V
CC
supplies to the device are stable in the
powered-up or powered-down conditions.
Hot Socketing Feature Implementation in MAX II Devices
The hot socketing feature turns off (tri-states) the output buffer during the power-up
event (either V
CCINT
or V
CCIO
supplies) or power-down event. The hot-socket circuit
generates an internal
HOTSCKT
signal when either V
CCINT
or V
CCIO
is below the
threshold voltage during power-up or power-down. The
HOTSCKT
signal cuts off the
output buffer to make sure that no DC current (except for weak pull-up leaking) leaks
through the pin. When V
CC
ramps up very slowly during power-up, V
CC
may still be
relatively low even after the power-on reset (POR) signal is released and device
configuration is complete.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤(pán)

  • 544-1964EPM240T100C5N-ND

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