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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

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3鈥?
Chapter 3: JTAG and In-System Programmability
In System Programmability
Table 3鈥?
shows the programming times for MAX II devices using in-circuit testers to
execute the algorithm vectors in hardware. Software-based programming tools used
with download cables are slightly slower because of data processing and transfer
limitations.
Table 3鈥?.
MAX II Device Family Programming Times
EPM240
EPM240G
EPM240Z
1.72
1.65
0.09
0.01
1.81
1.66
EPM570
EPM570G
EPM570Z
2.16
1.99
0.17
0.02
2.33
2.01
EPM1270
EPM1270G
2.90
2.58
0.30
0.03
3.20
2.61
EPM2210
EPM2210G
3.92
3.40
0.49
0.05
4.41
3.45
Description
Erase + Program (1 MHz)
Erase + Program (10 MHz)
Verify (1 MHz)
Verify (10 MHz)
Complete Program Cycle (1 MHz)
Complete Program Cycle (10 MHz)
Unit
sec
sec
sec
sec
sec
sec
UFM Programming
The Quartus II software, with the use of POF, Jam, or JBC files, supports
programming of the user flash memory (UFM) block independent of the logic array
design pattern stored in the CFM block. This allows updating or reading UFM
contents through ISP without altering the current logic array design, or vice versa. By
default, these programming files and methods will program the entire flash memory
contents, which includes the CFM block and UFM contents. The stand-alone
embedded Jam STAPL player and Jam Byte-Code Player provides action commands
for programming or reading the entire flash memory (UFM and CFM together) or
each independently.
f
For more information, refer to the
Using Jam STAPL for ISP via an Embedded Processor
chapter in the
MAX II Device Handbook.
In-System Programming Clamp
By default, the IEEE 1532 instruction used for entering ISP automatically tri-states all
I/O pins with weak pull-up resistors for the duration of the ISP sequence. However,
some systems may require certain pins on MAX II devices to maintain a specific DC
logic level during an in-field update. For these systems, an optional in-system
programming clamp instruction exists in MAX II circuitry to control I/O behavior
during the ISP sequence. The in-system programming clamp instruction enables the
device to sample and sustain the value on an output pin (an input pin would remain
tri-stated if sampled) or to explicitly set a logic high, logic low, or tri-state value on
any pin. Setting these options is controlled on an individual pin basis using the
Quartus II software.
f
For more information, refer to the
Real-Time ISP and ISP Clamp for MAX II Devices
chapter in the
MAX II Device Handbook.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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