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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

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2鈥?0
Chapter 2: MAX II Architecture
I/O Structure
Table 2鈥?.
Programmable Drive Strength
(Note 1)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Note to
Table 2鈥?:
(1) The I
OH
current strength numbers shown are for a condition of a V
OUT
= V
OH
minimum, where the V
OH
minimum
is specified by the I/O standard. The I
OL
current strength numbers shown are for a condition of a V
OUT
= V
OL
maximum, where the V
OL
maximum is specified by the I/O standard. For 2.5-V LVTTL/LVCMOS, the I
OH
condition is V
OUT
= 1.7 V and the I
OL
condition is V
OUT
= 0.7 V.
IOH/IOL Current Strength Setting (mA)
16
8
8
4
14
7
6
3
4
2
Slew-Rate Control
The output buffer for each MAX II device I/O pin has a programmable output slew-
rate control that can be configured for low noise or high-speed performance. A faster
slew rate provides high-speed transitions for high-performance systems. However,
these fast transitions may introduce noise transients into the system. A slow slew rate
reduces system noise, but adds a nominal output delay to rising and falling edges.
The lower the voltage standard (for example, 1.8-V LVTTL) the larger the output
delay when slow slew is enabled. Each I/O pin has an individual slew-rate control,
allowing the designer to specify the slew rate on a pin-by-pin basis. The slew-rate
control affects both the rising and falling edges.
Open-Drain Output
MAX II devices provide an optional open-drain (equivalent to open-collector) output
for each I/O pin. This open-drain output enables the device to provide system-level
control signals (for example, interrupt and write enable signals) that can be asserted
by any of several devices. This output can also provide an additional wired-OR plane.
Programmable Ground Pins
Each unused I/O pin on MAX II devices can be used as an additional ground pin.
This programmable ground feature does not require the use of the associated LEs in
the device. In the Quartus II software, unused pins can be set as programmable GND
on a global default basis or they can be individually assigned. Unused pins also have
the option of being set as tri-stated input pins.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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