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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

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2鈥?6
Chapter 2: MAX II Architecture
Global Signals
The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.
The UFM block connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. This block also has DirectLink
interconnects for fast connections to and from a neighboring LAB. For more
information about the UFM interface to the logic array, see
鈥淯ser Flash Memory
Block鈥?on page 2鈥?8.
Table 2鈥?
shows the MAX II device routing scheme.
Table 2鈥?.
MAX II Device Routing Scheme
Destination
Source
LUT Chain
Register Chain
Local
Interconnect
DirectLink
Interconnect
R4 Interconnect
C4 Interconnect
LE
UFM Block
Column IOE
Row IOE
Note to
Table 2鈥?:
(1) These categories are interconnects.
LUT
Chain
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v
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Register
Chain
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v
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Local
(1)
鈥?/div>
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v
v
v
v
v
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DirectLink
(1)
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v
v
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v
R4
(1)
鈥?/div>
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v
v
v
v
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v
C4
(1)
鈥?/div>
鈥?/div>
鈥?/div>
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v
v
v
v
v
v
LE
v
v
v
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鈥?/div>
鈥?/div>
鈥?/div>
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UFM
Block
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v
鈥?/div>
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Column
IOE
鈥?/div>
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v
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v
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Row
IOE
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v
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v
鈥?/div>
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Fast I/O
(1)
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v
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Global Signals
Each MAX II device has four dual-purpose dedicated clock pins (GCLK[3..0], two
pins on the left side and two pins on the right side) that drive the global clock network
for clocking, as shown in
Figure 2鈥?3.
These four pins can also be used as general-
purpose I/O if they are not used to drive the global clock network.
The four global clock lines in the global clock network drive throughout the entire
device. The global clock network can provide clocks for all resources within the
device including LEs, LAB local interconnect, IOEs, and the UFM block. The global
clock lines can also be used for global control signals, such as clock enables,
synchronous or asynchronous clears, presets, output enables, or protocol control
signals such as
TRDY
and
IRDY
for PCI. Internal logic can drive the global clock
network for internally-generated global clocks and control signals.
Figure 2鈥?3
shows
the various sources that drive the global clock network.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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