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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

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2鈥?4
Chapter 2: MAX II Architecture
MultiTrack Interconnect
functions from LE 1 to LE 10 in the same LAB. The register chain connection allows
the register output of one LE to connect directly to the register input of the next LE in
the LAB for fast shift registers. The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
Figure 2鈥?1
shows the LUT chain and register chain interconnects.
Figure 2鈥?1.
LUT Chain and Register Chain Interconnects
Local Interconnect
Routing Among LEs
in the LAB
LUT Chain
Routing to
Adjacent LE
LE0
Register Chain
Routing to Adjacent
LE's Register Input
LE1
Local
Interconnect
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
The C4 interconnects span four LABs up or down from a source LAB. Every LAB has
its own set of C4 interconnects to drive either up or down.
Figure 2鈥?2
shows the C4
interconnect connections from an LAB in a column. The C4 interconnects can drive
and be driven by column and row IOEs. For LAB interconnection, a primary LAB or
its vertical LAB neighbor can drive a given C4 interconnect. C4 interconnects can
drive each other to extend their range as well as drive row interconnects for column-
to-column connections.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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