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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 1035.40KB

  • 101頁

  • Altera   Altera

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Chapter 2: MAX II Architecture
Logic Elements
2鈥?1
The speed advantage of the carry-select chain is in the parallel precomputation of
carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE
is in the critical path. Only the propagation delays between LAB carry-in generation
(LE 5 and LE 10) are now part of the critical path. This feature allows the MAX II
architecture to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
Figure 2鈥?
shows the carry-select circuitry in an LAB for a 10-bit full adder. One
portion of the LUT generates the sum of two bits using the input signals and the
appropriate carry-in bit; the sum is routed to the output of the LE. The register can be
bypassed for simple adders or used for accumulator functions. Another portion of the
LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for
the addition of given inputs. The carry-in signal for each chain,
carry-in0
or
carry-in1,
selects the carry-out to carry forward to the carry-in signal of the next-
higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local,
row, or column interconnects.
Figure 2鈥?.
Carry-Select Chain
LAB Carry-In
A1
B1
A2
B2
0
LE0
1
Sum1
LAB Carry-In
Carry-In0
Carry-In1
LE1
Sum2
LUT
data1
data2
Sum
LUT
A3
B3
A4
B4
LE2
Sum3
LE3
Sum4
LUT
A5
B5
LE4
Sum5
LUT
0
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
LE5
1
Sum6
Carry-Out0
Carry-Out1
LE6
Sum7
LE7
Sum8
LE8
Sum9
LE9
Sum10
To top of adjacent LAB
LAB Carry-Out
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5N 產品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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