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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁

  • Altera   Altera

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Chapter 2: MAX II Architecture
Logic Elements
2鈥?
Normal Mode
The normal mode is suitable for general logic applications and combinational
functions. In normal mode, four data inputs from the LAB local interconnect are
inputs to a four-input LUT (see
Figure 2鈥?).
The Quartus II Compiler automatically
selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use
LUT chain connections to drive its combinational output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the data3 input of the LE.
LEs in normal mode support packed registers.
Figure 2鈥?.
LE in Normal Mode
sload
sclear
(LAB
Wide)
(LAB
Wide)
Register chain
connection
aload
(LAB
Wide)
addnsub (LAB
Wide)
(1)
data1
data2
data3
cin (from cout
of previous LE)
data4
4-Input
LUT
ALD/PRE
ADATA Q
D
ENA
CLRN
Row, column, and
DirectLink routing
Row, column, and
DirectLink routing
clock (LAB
Wide)
ena (LAB
Wide)
aclr (LAB
Wide)
Local routing
LUT chain
connection
Register
chain output
Register Feedback
Note to
Figure 2鈥?:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic
mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first
two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the
other two LUTs generate carry outputs for the two chains of the carry-select circuitry.
As shown in
Figure 2鈥?,
the LAB carry-in signal selects either the
carry-in0
or
carry-in1 chain. The selected chain鈥檚 logic level in turn determines which parallel sum
is generated as a combinational or registered output. For example, when
implementing an adder, the sum output is the selection of two possible calculated
sums:
data1 + data2 + carry in0
or
data1 + data2 + carry-in1
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1964EPM240T100C5N-ND

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