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EPM240T100C5N Datasheet

  • EPM240T100C5N

  • MAX II ISP CPLD 240, TQFP100, 240; CPLD Type:FLASH; No. of M...

  • 101頁(yè)

  • Altera   Altera

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2鈥?
Chapter 2: MAX II Architecture
Logic Array Blocks
Logic Array Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,
a look-up table (LUT) chain, and register chain connection lines. There are 26 possible
unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE
outputs in the same LAB. The local interconnect transfers signals between LEs in the
same LAB. LUT chain connections transfer the output of one LE鈥檚 LUT to the adjacent
LE for fast sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE鈥檚 register to the adjacent LE鈥檚 register
within an LAB. The Quartus
廬
II software places associated logic within an LAB or
adjacent LABs, allowing the use of local, LUT chain, and register chain connections
for performance and area efficiency.
Figure 2鈥?
shows the MAX II LAB.
Figure 2鈥?.
MAX II LAB Structure
Row Interconnect
Column Interconnect
LE0
Fast I/O connection
to IOE
(1)
DirectLink
interconnect from
adjacent LAB
or IOE
LE1
LE2
LE3
LE4
LE5
LE6
DirectLink
interconnect to
adjacent LAB
or IOE
LE7
LE8
LE9
Logic Element
LAB
Local Interconnect
DirectLink
interconnect to
adjacent LAB
or IOE
Fast I/O connection
to IOE
(1)
DirectLink
interconnect from
adjacent LAB
or IOE
Note to
Figure 2鈥?:
(1) Only from LABs adjacent to IOEs.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB local
interconnect is driven by column and row interconnects and LE outputs within the
same LAB. Neighboring LABs, from the left and right, can also drive an LAB鈥檚 local
interconnect through the DirectLink connection. The DirectLink connection feature
minimizes the use of row and column interconnects, providing higher performance
and flexibility. Each LE can drive 30 other LEs through fast local and DirectLink
interconnects.
Figure 2鈥?
shows the DirectLink connection.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5N 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤(pán)

  • 544-1964EPM240T100C5N-ND

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