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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁(yè)

  • Altera   Altera

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Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5鈥?9
Table 5鈥?4
shows the external I/O timing parameters for EPM570 devices.
Table 5鈥?4.
EPM570 Global Clock External I/O Timing Parameters
鈥? Speed
Grade
Symbol
t
PD1
Parameter
Worst case pin-to-pin
delay through 1 look-
up table (LUT)
Best case pin-to-pin
delay through 1 LUT
Global clock setup
time
Global clock hold
time
Global clock to
output delay
Global clock high
time
Global clock low time
Minimum global
clock period for
16-bit counter
Maximum global
clock frequency for
16-bit counter
Condition
10 pF
Min
鈥?/div>
Max
5.4
鈥? Speed
Grade
Min
鈥?/div>
Max
7.0
鈥? Speed
Grade
Min
鈥?/div>
Max
8.7
鈥? Speed
Grade
Min
鈥?/div>
Max
9.5
鈥? Speed
Grade
Min
鈥?/div>
Max
15.1
Unit
ns
t
PD2
t
SU
t
H
t
CO
t
CH
t
CL
t
CNT
10 pF
鈥?/div>
鈥?/div>
10 pF
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.2
0.0
2.0
166
166
3.3
3.7
鈥?/div>
鈥?/div>
4.5
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.5
0.0
2.0
216
216
4.0
4.8
鈥?/div>
鈥?/div>
5.8
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
1.9
0.0
2.0
266
266
5.0
5.9
鈥?/div>
鈥?/div>
7.1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
2.6
0
2.0
253
253
5.4
5.7
鈥?/div>
鈥?/div>
6.1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
4.5
0
2.0
335
335
8.1
7.7
鈥?/div>
鈥?/div>
7.6
鈥?/div>
鈥?/div>
鈥?/div>
ns
ns
ns
ns
ps
ps
ns
f
CNT
鈥?/div>
鈥?/div>
304.0
(1)
鈥?/div>
247.5
鈥?/div>
201.1
鈥?/div>
184.1
鈥?/div>
123.5
MHz
Note to
Table 5鈥?4:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock
input pin maximum frequency.
Table 5鈥?5
shows the external I/O timing parameters for EPM1270 devices.
Table 5鈥?5.
EPM1270 Global Clock External I/O Timing Parameters (Part 1 of 2)
鈥? Speed Grade
Symbol
t
PD1
Parameter
Worst case pin-to-pin
delay through 1 look-up
table (LUT)
Best case pin-to-pin
delay through 1 LUT
Global clock setup time
Global clock hold time
Global clock to output
delay
Global clock high time
Global clock low time
Condition
10 pF
Min
鈥?/div>
Max
6.2
鈥? Speed Grade
Min
鈥?/div>
Max
8.1
鈥? Speed Grade
Min
鈥?/div>
Max
10.0
Unit
ns
t
PD2
t
SU
t
H
t
CO
t
CH
t
CL
10 pF
鈥?/div>
鈥?/div>
10 pF
鈥?/div>
鈥?/div>
鈥?/div>
1.2
0.0
2.0
166
166
3.7
鈥?/div>
鈥?/div>
4.6
鈥?/div>
鈥?/div>
鈥?/div>
1.5
0.0
2.0
216
216
4.8
鈥?/div>
鈥?/div>
5.9
鈥?/div>
鈥?/div>
鈥?/div>
1.9
0.0
2.0
266
266
5.9
鈥?/div>
鈥?/div>
7.3
鈥?/div>
鈥?/div>
ns
ns
ns
ns
ps
ps
漏 Novermber 2008 Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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