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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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上傳產(chǎn)品規(guī)格書

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Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5鈥?7
Figure 5鈥?.
UFM Erase Waveform
ARShft
ARClk
ARDin
DRShft
DRClk
DRDin
DRDout
OSC_ENA
Program
Erase
Busy
t
EB
t
EPMX
t
BE
t
OSCS
t
OSCH
t
ADS
t
ASU
t
ACLK
9 Address Bits
t
AH
t
ADH
Table 5鈥?2.
Routing Delay Internal Timing Microparameters
鈥? Speed
Grade
Routing
t
C4
t
R4
t
LOCAL
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
429
326
330
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
556
423
429
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
687
521
529
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
(1)
(1)
(1)
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
(1)
(1)
(1)
Unit
ps
ps
ps
Note to
Table 5鈥?2:
(1) The numbers will only be available in a later revision.
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in
Table 5鈥?7
through
Table 5鈥?8.
f
For more information about each external timing parameters symbol, refer to the
Understanding Timing in MAX II Devices
chapter in the
MAX II Device Handbook.
漏 Novermber 2008 Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD(復(fù)雜可編程邏輯器件)

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V,3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP(14x14)

  • 托盤

  • 544-1146

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